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Insert gap between 555 monostable output pulses

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pmolsen

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I have a standard monostable 555 pulse stretcher like this one: http://www.555-timer-circuits.com/monostable-555.html It outputs a pulse of around 100ms, which drives the gate of a logic level mosfet (IRLB8721).

There are continual input pulses in bursts of varying lengths, with the result that the output effectively stays on for the duration. I want to force the output low for at least 100ms after each 100mm output pulse. I do not want to delay the turn-on initially, just force a delay at the end of each pulse.

Is there any simple method of achieving that other than by using a second 555 please.
 

crutschow

Well-Known Member
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So you are saying there are input trigger pulses that occur right after the 100ms period that you want to ignore for another 100ms?
How fast do these input pulses occur?

I don't see how to suppress them without adding another 555.
 

pmolsen

New Member
That is correct. They occur at random speeds and lengths up to around 1 second with random gaps between. I was hoping that the mosfet could charge a cap that discharges slowly and somehow does not allow the new timing cycle to start until it has fully discharged.

A theoretical method would be something like having the cap turn on a transistor which holds on a relay for a short while and the relay disconnects the incoming connection to the 555 trigger pin 2. I don't want to use an actual relay though.
 
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dknguyen

Well-Known Member
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I was hoping that the mosfet could charge a cap that discharges slowly and somehow does not allow the new timing cycle to start until it has fully discharged.
Many have hoped this, none have succeeded.

Caps discharge slow. MOSFETs can be halfway on and don't have clear thresholds. Not good. If you add a comparator then you might as well add a 555.
 

AnalogKid

Well-Known Member
Most Helpful Member
Since you don't need the 555 high current output stage, I'd use one CD4093 quad Schmitt NAND gate to do both the main output pulse and the inhibit timer. The leading edge of a positive-going input pulse triggers the main output, a positive-going output pulse. The trailing edge of the output pulse drives a second R-C timer that inhibits the main input through a NAND gate. With two R-C networks, the output pulse width and the inhibit time are completely independent. And, fewer parts than two 555's.

Whipping out a schematic is a bit cumbersome these days, but I'll try to post one tomorrow.

ak
 
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