Indexed Addressing

[Dakta]

Just wondering if someone can clear up what I think should be a quick misunderstanding on how rom is addressed in a particular instance.

I don't know too much about the 8051, but I know a little about controllers in general.

Anyway, basic story is, I have the source for a controller which I'm trying to understand, which uses on-chip rom for several lookup tables, however trying to trace some of the table lookups, I'm a bit confused.

I'm at work so I don't have a exact code listing, but from memory the table calls look something like this:

MOV DPTR,#[B]F[/B]674h
MOVC	 A,@A+DPTR

I don't know if that's 100% correct but the idea is you put a base address in the datapointer, put an offset (or the nth value you are looking for) in the accumulator, then move the value held in the address of datapointer+A into the accumulator, where presumably you can then work on the retreived value as your situation warrants.

My question is this, if you look at the direct address (F674) I used as the base of the table, that confuses me. Because the chip size used to hold the program and data only goes up to 7FFF.

I'm sure it's a misunderstanding on my part, and possibly related to the 16 bit nature of the datapointer.

I mean, I don't want to sound daft, but could I be misunderstanding the byte ordering? Could it be 74F6 for example, rather than F674?

I'd feel stupid if that was the reason but... I only thought of that now, and I'm at work so I can't quicly check.

 

[Gary B]

Your question implies that you think the ROM address start at #0000h. There is no reason why the manufacturer didn’t map it to #8000h as the start address instead. Especially since you state it is a 32K ROM and 64K addressable space.

I am not familiar with the specific chip so I can’t be sure but, I suspect that they mapped it to the top of addressable memory so you could put your operating program in low memory and have the maximum amount of contiguous space available for your application.

 

[Dakta]

Right, that complicates things.

is there any way to try and deduce the correct settings?

Interesting reply, I'll admit it does not currently make sense to me.

I just assumed that since we had a chip with space of 0x000 -> 0x7FFF, where the data held (on EPROM) in each address holds either data or code. Clearly that isn't the case, but now I've lost my bearings

 

[Gary B]

I used to mess with 8008 and Z80 8-bit processors. The restart address was not at 0x0000 but, something higher leaving the low addresses available for the interrupt line restart addresses and normally accessed RAM that would have the program loaded from some external source. Controllers, or at least the ones I remember reading the specs on, have the program and lookup tables on a ROM in high memory that is copied into RAM that is mapped into the low address space where it runs. That is done because RAM is faster than a ROM read cycle. Some of them even switched out the ROM after copying it and switched in more RAM.