zkt_PiratesDen
New Member
This has had me stumped for a couple of days. Hoping someone can point out he error in my ways. I have a pic 16f87 contriling a tda 7439ds sound prosessor chip with I2C protocol. Since the requirements are rather simple the pic I2C registers are not being used. Instead the scl line is controled by portb.7 and sda by porta.7 with 10k pullup resistors on the pins.The pic code is straight line (sequential) - just one thing after the other, except for loops to shift the data to the sda line. Easier to read and less to go wrong. Yet something has, or I`m misunderstanding the tda datasheet. The code should switch the tda`s input from input2 to input4. The scope indicates the chip is working properly but not switching. The pic sends a start condition, then three 8 bit words, then a stop condition on sda. The start condition is a high to low transition on sda while scl is high. The stop condition is a low to high transition on sda while scl is high. Data is allowed to change only when scl is low and must remain stable while scl is high. The tda sends an acknowledgement bit following each 8 bit word during the 9th clock pulse bit by pulling the sda line low.
Please refer to the dta datasheet, pages 8 & 9 for the timing diagrams and word format to verify this:
**broken link removed**
Scope shows that there is a clock signal on the scl line and data on the sda line but NO ack pulse.There should be an ack atfer each word the pic sends.(three words: addr- $88, sub_adr-$00, data-$00). I suspected that the tda chip might have been damages so connected a new one- same results. The test circuit is as shown in the dataasheet ancept the rc equalizer omponents are omitted. the output is taken from the muxout. Hopefully there is something simple and obvious that I have overlooked- I`m pretty good at that. thanks much for your time and trouble
The variables that arent used are part of another part of the program that isnt posted for simplicitys sake.Also - ignore the comments except the ones that describe the input pins
zkt
Please refer to the dta datasheet, pages 8 & 9 for the timing diagrams and word format to verify this:
**broken link removed**
Scope shows that there is a clock signal on the scl line and data on the sda line but NO ack pulse.There should be an ack atfer each word the pic sends.(three words: addr- $88, sub_adr-$00, data-$00). I suspected that the tda chip might have been damages so connected a new one- same results. The test circuit is as shown in the dataasheet ancept the rc equalizer omponents are omitted. the output is taken from the muxout. Hopefully there is something simple and obvious that I have overlooked- I`m pretty good at that. thanks much for your time and trouble
The variables that arent used are part of another part of the program that isnt posted for simplicitys sake.Also - ignore the comments except the ones that describe the input pins
Code:
program rc5
' pic 16F87
dim dly_half_period,n,tmp,addr,data,which_byte,scl,sda as byte
const tda_adr=$88 'array for all
dim tda_sub_adr,tda_data as byte
' portb.0-5: display
' portb.6: input pin
' portb.7 scl
' porta.7 sda
main:
osccon=%01100010
while iofs=1
wend
cmcon=7
trisa=32
trisb=64
portb=%10111111
porta=128
't2con.t2ckps1=1
t2con.t2ckps1=0
dly_half_period=0
tmp=0
n=12
addr=0
data=0
which_byte=0
start:
tda_data=$00000000 'tda_data 10=in2 00=in4
tda_sub_adr=%00000000
scl=%10000000
portb = scl and 128 'scl=high
sda=%10000000
porta = sda and 128 'sda=high
sda=%00000000 '(scl=high)
porta=sda and 128 'sda=low
pir1.tmr2if=0
't2con.t2ckps1=1
t2con.t2ckps1=0
while pir1.tmr2if=0
wend
adr:
for n=0 to 7
scl=%00000000
portb=scl and 128 'sda change
delay_ms(10)
if portb.7=0 then
tmp=tda_adr
tmp=tmp<<n
porta=tmp and 128
end if
pir1.tmr2if=0
t2con.tmr2on=1
'con.t2ckps1=1
t2con.t2ckps1=0
while pir1.tmr2if=0
wend
scl=%10000000 'scl=high
portb=scl and 128
pir1.tmr2if=0
t2con.tmr2on=1
't2con.t2ckps1=1
t2con.t2ckps1=0
while pir1.tmr2if=0
wend
next n
'skip_9th_scl_bit
trisa=(32+128) 'switch scl snd sda lines to inp
scl= %00000000 'scl=low
portb=scl and 128
pir1.tmr2if=0
t2con.tmr2on=1
't2con.t2ckps1=1
t2con.t2ckps1=0
while pir1.tmr2if=0
wend
scl=%10000000 'scl= high
portb=scl and 128
pir1.tmr2if=0
t2con.tmr2on=1
't2con.t2ckps1=1
t2con.t2ckps1=0
while pir1.tmr2if=0
wend
trisa=32
sub_adr:
for n=0 to 7
scl=%00000000
portb=scl and 128 'sda change
delay_ms(10)
if portb.7=0 then
tmp=tda_sub_adr
tmp=tmp<<n
porta=tmp and 128
end if
pir1.tmr2if=0
t2con.tmr2on=1
'con.t2ckps1=1
t2con.t2ckps1=0
while pir1.tmr2if=0
wend
scl=%10000000 'scl=high
portb=scl and 128
pir1.tmr2if=0
t2con.tmr2on=1
't2con.t2ckps1=1
t2con.t2ckps1=0
while pir1.tmr2if=0
wend
next n
'skip_9th_scl_bit
trisa=(32+128) 'switch scl snd sda lines to inp
scl= %00000000 'scl=low
portb=scl and 128
pir1.tmr2if=0
t2con.tmr2on=1
't2con.t2ckps1=1
t2con.t2ckps1=0
while pir1.tmr2if=0
wend
scl=%10000000 'scl= high
portb=scl and 128
pir1.tmr2if=0
t2con.tmr2on=1
't2con.t2ckps1=1
t2con.t2ckps1=0
while pir1.tmr2if=0
wend
data:
for n=0 to 7
scl=%00000000
portb=scl and 128 'sda change
delay_ms(10)
if portb.7=0 then
tmp=tda_data
tmp=tmp<<n
porta=tmp and 128
end if
pir1.tmr2if=0
t2con.tmr2on=1
'con.t2ckps1=1
t2con.t2ckps1=0
while pir1.tmr2if=0
wend
scl=%10000000 'scl=high
portb=scl and 128
pir1.tmr2if=0
t2con.tmr2on=1
't2con.t2ckps1=1
t2con.t2ckps1=0
while pir1.tmr2if=0
wend
next n
'skip_9th_scl_bit
trisa=(32+128) 'switch scl snd sda lines to inp
scl= %00000000 'scl=low
portb=scl and 128
pir1.tmr2if=0
t2con.tmr2on=1
't2con.t2ckps1=1
t2con.t2ckps1=0
while pir1.tmr2if=0
wend
scl=%10000000 'scl= high
portb=scl and 128
pir1.tmr2if=0
t2con.tmr2on=1
't2con.t2ckps1=1
t2con.t2ckps1=0
while pir1.tmr2if=0
wend
stop:
sda=%10000000
porta = sda and 128 'sda=high
sda=%00000000 '(scl=high)
porta=sda and 128 'sda=low
pir1.tmr2if=0
't2con.t2ckps1=1
t2con.t2ckps1=0
while pir1.tmr2if=0
wend
scl= %00000000 'scl=low
portb=scl and 128
pir1.tmr2if=0
t2con.tmr2on=1
't2con.t2ckps1=1
t2con.t2ckps1=0
while pir1.tmr2if=0
wend
zkt
Last edited: