I want to design using by cascading 74*163 ic

[atakan]

I want to design such as 33,34,35,36,37,38......74,75,76,77 and finishing.
how can i do this? below has a image, is it true or false?

 

[atakan]

is it true?

 

[Ian Rogers]

Wow... What schematic editor is that.... The points aren't even connected to the nand gate..

You need to write a bit more.. ie Do you need to start a count at 33 and run until 77 and reset??

 

[atakan]

Yes i need. start 33 and finish 77

 

[atakan]

Wow... What schematic editor is that.... The points aren't even connected to the nand gate..

You need to write a bit more.. ie Do you need to start a count at 33 and run until 77 and reset??

yes i need. start 33 and 77 finish

 

[MikeMl]

'163 is a synchronous binary up-counter with synch. pre-load.

Step 1. Figure out how to connect two cascaded '163s so that they would naturally count 0 to 255. See the data sheet

Step 2. Wire the two sets of ABCD inputs to the pattern 33 (00100001)

Step 2. Decode state 77 (01001101). Looks like it will take a four input gate to do that...

Step 3. Use the gate output to control the Load input(s) so that the counter naturally transitions from 77 to 33 on the 45th clock cycle.

Note that it will take extra logic to preset the counter on power up. If you dont, the counter could power-up in any state between 0 and 255, meaning it will take a random number of clock cycles (up to 255-45) before it gets into the 33-77 sequence.

 

[atakan]

'163 is a synchronous binary up-counter with synch. pre-load.

Step 1. Figure out how to connect two cascaded '163s so that they would naturally count 0 to 255. See the data sheet

Step 2. Wire the two sets of ABCD inputs to the pattern 33 (00100001)

Step 2. Decode state 77 (01001101). Looks like it will take a four input gate to do that...

Step 3. Use the gate output to control the Load input(s) so that the counter naturally transitions from 77 to 33 on the 45th clock cycle.

Note that it will take extra logic to preset the counter on power up. If you dont, the counter could power-up in any state between 0 and 255, meaning it will take a random number of clock cycles (up to 255-45) before it gets into the 33-77 sequence.

thank you very much 77 output connect to load okay. where is connecting 33 ? and is rco empty ?

 

[atakan]

'163 is a synchronous binary up-counter with synch. pre-load.

Step 1. Figure out how to connect two cascaded '163s so that they would naturally count 0 to 255. See the data sheet

Step 2. Wire the two sets of ABCD inputs to the pattern 33 (00100001)

Step 2. Decode state 77 (01001101). Looks like it will take a four input gate to do that...

Step 3. Use the gate output to control the Load input(s) so that the counter naturally transitions from 77 to 33 on the 45th clock cycle.

Note that it will take extra logic to preset the counter on power up. If you dont, the counter could power-up in any state between 0 and 255, meaning it will take a random number of clock cycles (up to 255-45) before it gets into the 33-77 sequence.

 

[MikeMl]

...where is connecting 33 ?

To the ABCD,ABCD inputs of the two counters. Step 2.

and is rco empty ?

This is part of cascading the two 4bit counters to make a single 8bit counter. Step 1.