Hi,
In the attached hi side fet gate drive circuit, do you know how I can prevent so much off-state current flow in D3 and R16?
I dont wish to reduce the value of R16 as i need high base current so i get high collector current.
(LTspice simulation and jpeg scm attached)
In the attached hi side fet gate drive circuit, do you know how I can prevent so much off-state current flow in D3 and R16?
I dont wish to reduce the value of R16 as i need high base current so i get high collector current.
(LTspice simulation and jpeg scm attached)