How is the diode working here

[haxxx]

A little help fro u Pro's out there.
I found the attached circuit
over by the home.cogeco.ca/ website.
I'm curious as to what he means when he
says the diode will allow the capacitor to discharge.
shouldn't it discharge through the 100k?

Hx.

 

[ccurtis]

When power is turned off, VCC and ground are at the same voltage, so you can draw an imaginary wire from VCC to ground and see that the positive side of the capacitor is connected to ground and the negative side of the capacitor is connected to the base of the transistor. Ergo, base-emitter junction of the transistor is reverse biased, diode is forward biased.

 

[MikeMl]

When power is turned off, VCC and ground are at the same voltage, ...

Pretty big assumption. More like C1 discharges through D1 and all of the resistive paths connected between VCC and Ground. If the only thing that was connected to the power supply was the pictured circuit, then the discharge time constant would be determined primarily by how long the 555 runs on the energy stored in C1. The three resistors that determine the comparitor trip points inside the 555 are range from 30K to 300K, so the discharge time of C1 could be pretty long.

 

[ccurtis]

VCC of zero is the ultimate end, regardless of how long it takes to get there. Whether one draws an imaginary wire between VCC and ground, or the equivalent resistance of the discharge paths between VCC and ground with power disconnected, the biasing of the transistor and diode is the same. Only the amount of time it takes to discharge differs between the two cases.

 

[haxxx]

Ok I'm self taught so bear with me here,
The Positive side of the capacitor goes to ground, but what is happening at the negative side. Doesn't the anode of the diode need to be more positive than the cathode for it to be forward biased?

 

[ccurtis]

Ok I'm self taught so bear with me here,
The Positive side of the capacitor goes to ground, but what is happening at the negative side. Doesn't the anode of the diode need to be more positive than the cathode for it to be forward biased?

The negative side of the capacitor reaches .6V after it gets finished charging after power is applied. So, the plus side of the capacitor is at VCC and the negative side is only at .6V. When power is turned off the positive side of the capacitor discharges through the anode of the diode back to its negative side which is at a lower voltage than its positive side.

 

[MikeMl]

Think of it slightly differently. The negative end of the capacitor is clamped one diode drop (≈0.65V) below ground. Ground is always ground

Because you cannot change the voltage on a capacitor in zero time, right after the input to the supply is turned off, C1 (and the filter capacitor in the powersupply) holds Vcc at almost the previous supply voltage. C1, and the supply's filter caps slowly discharge toward ground. When the dust settles several seconds later, C1 and the supply's filter capacitor are both left discharged...

 

[haxxx]

Thanks a lot guys.

HX.

 

[haxxx]

One more very important question!

During the regular operation of my circuit I will need to periodically
send pin 4 low. Is it ok fo me to put a OR gate between
C1 and R1 so i can turn on the transistor.

Thnx again.

 

[ccurtis]

During the regular operation of my circuit I will need to periodically send pin 4 low. Is it ok fo me to put a OR gate between C1 and R1 so i can turn on the transistor.

To send pin 4 low, I suggest doing it directly at pin 4 using the open collector of a second transistor, an open collector/drain logic gate output, or other switch. If using a second transistor, the emitter of the second transistor is connected to ground and you bring pin 4 low by applying enough base current to the second transistor to saturate it.

 

[indulis]

As MikeMI says, “pretty big assumption”. Zero volts and ground are not the same thing. But for the sake of argument, suppose we were to say that Vcc did go to ground (a leftover from learning superposition in school I guess), then when power is turned off, the D1, C1 node would, relative to ground, go to minus Vcc. Now D1 is forward biased and discharges C1 thru the Vcc source.

P.S. MikeMI... like the plane, I fly a 172S (rented) out of 1B9.

 

[MikeMl]

...
P.S. MikeMI... like the plane, I fly a 172S (rented) out of 1B9.

3400 hours in my 182 and counting. APRS Track from my last flight, last Friday:

 

[ericgibbs]

Think of it slightly differently. The negative end of the capacitor is clamped one diode drop (≈0.65V) below ground. Ground is always ground

Because you cannot change the voltage on a capacitor in zero time, right after the input to the supply is turned off, C1 (and the filter capacitor in the powersupply) holds Vcc at almost the previous supply voltage. C1, and the supply's filter caps slowly discharge toward ground. When the dust settles several seconds later, C1 and the supply's filter capacitor are both left discharged...

hi MIke,
The circuit description on the posted drawing is for a power ON, RESET pulse.

At power up, the cap charges via the diode and the positive Vbe switches on the transistor which pulls the common RESET low.
When the cap is charged the Vbe ON disappears and the RESET line goes high.

IMO a 10K from the RESET pin to +V and 1uF cap to 0V would be just as effective and is commonly used.

 

[MikeMl]

hi MIke,
The circuit description on the posted drawing is for a power ON, RESET pulse.

I agree. Q1 is turned on, and generates the RESET while the capacitor is CHARGING.

At power up, the cap charges via the diode ...

Negative. The capacitor charges thought the Base-to-Emitter junction of Q1. The diode is reversed biased during charging. The diode is there ONLY to discharge the capacitor when the circuit is de-powered, in order to reset the timing network for the NEXT power-up sequence. The OP was asking about the purpose of the diode.

... When the cap is charged the Vbe ON disappears and the RESET line goes high.

IMO a 10K from the RESET pin to +V and 1uF cap to 0V would be just as effective and is commonly used.

The duration of the reset pulse would be much shorter that way, 6ms vs about 60ms the way the posted circuit does it. The reason you might want the longer time constant is because the turn-on slew rate of the main power supply might be slower than 6ms, therefore you want the RESET pulse to be there longer than it takes the supply to come up.

 

[haxxx]

The duration of the reset pulse would be much shorter that way, 6ms vs about 60ms the way the posted circuit does it. The reason you might want the longer time constant is because the turn-on slew rate of the main power supply might be slower than 6ms, therefore you want the RESET pulse to be there longer than it takes the supply to come up.

Would there be any danger in just increasing the value of the resistor
and/or capacitor to get a longer time constant.

Haxxx.

 

[MikeMl]

Would there be any danger in just increasing the value of the resistor
and/or capacitor to get a longer time constant.

Haxxx.

To reset the NE555 or LM555, you have to sink 0.4 to 1.5mA to Vss(gnd) to pull the RESET pin low. This is a strike against trying to hang an RC network directly on pin 4. The CMOS versions of the 555 do not have this issue.

As long as you are using the transistor to sink the RESET pin current, then if you want a longer time constant, make C bigger, but do not increase the base resistor much beyond 100K.

 

[ericgibbs]

Would there be any danger in just increasing the value of the resistor
and/or capacitor to get a longer time constant.

Haxxx.

hi,
No problem in increasing the cap value, within sensible limits in order to get the required reset time.

With CMOS versions its also OK to increase the value of the charging resistor.

 

[haxxx]

Thanks a lot guys

Haxxx.