I think there is a hole in the logic where depending on the FET threshold voltage the motor can be in current limit without tripping the first logic gate
I think you've hit the nail on the head there, Ron. I've now looked into this a bit more. Re-visiting the datasheet for the IRF3205 which Joe is using, the graphs show that for a 'typical' 3205 with Vgs = 4.5 the Vds is ~ 0.2V for a drain current of 3A. In other words the FET isn't fully turned on at Vgs = 4.5V. Even so, it would cause Q1 to pull the U1 input down
just below the Schmitt threshold (using your example of the thresholds being 6V +- 1.5V) and trip the latch. So operation is marginal.
However, Joe's FET examples won't be 'typical'

. Looks like they need a slightly higher Vgs to turn them on enough to give ~3A and cause the motor to run. In which case they won't necessarily get U1 input below the trip point and will leave the motor in a twilight zone, as is now happening.
Three options occur to me to overcome this and make tripping more dependable:
1) replace the FETs with logic-level types,
2) use an op-amp instead of Q1 to set the trip,
3) add another transistor stage.
Option 1 could be expensive; option 2 would mean quite a change to the circuit layout; option 3 seems simplest with least change to the layout.
Here's option 3....PDM_Mk11 :
View attachment 67938
In this circuit the component changes are within the dotted-line. Q3 and R11/12 have been added and U1d is now redundant (but it's inputs need to be connected to +12 or ground, whichever is convenient).
I've run a sim on this using various FET models, plus forcing various voltage levels on Q1 collector. The circuit should now trip when Q1 collector is anywhere within the 2-10V range, so should cope with almost any N-FET.
Edit:
Could just make the time out a little shorter than the fastest cycle time?
A possibility; but a shorter time would raise the average power dissipation in the FET, which is already pretty high when the trip kicks in.