I have had a slightly longer look at your circuit now and have a better understanding of the design. From the SCR data sheet I now know that the LEDs can't be high power, but if you could let me know roughly what the LED current are, that would help.
Here are my second thoughts:
(1) You may be surprised, but the original 'simplest circuit' (SC) is better for this application. While the diode bridge will half the ripple across C1, it does mean that the bottom of C1, effectively system OV, will have a square wave on it of 600mv to -600mV with respect to the neutral line of the mains supply. This is generated by the forward drop of diodes 3/4 and 2/4 and won't stop the circuit from working but it is undesirable. While the ripple is double with the SC, it should be fine for this circuit and it eliminates three diodes involved with the mains so it reduces cost, increases reliability and increases safety.
Apart from the above, I can't see any problems with either power supply arrangements that would allow mains voltage spikes to cause a malfunction or damage the chip. In fact, both approaches give exceptional protection. I now would advise to stay with the power supply arrangements of SC, in spite of what I said previously about using an off-line SMPS.
Your idea of putting a 4V7 Zener diode across C1 is spot on and is a good precaution in case the voltage across C1 tried to rise too high. A ceramic capacitor, or other high frequency type, across C1, would be another good idea. 100nF would be ideal but any value above 10nF would be fine.
(2) The clock arrangement is a worry. As the clock input is derived from the mains via a 2M2 resistor, it is feeding a +-141uA (311V peak/2M2M Ohms) peak constant AC current into the chip clock input. In theory this may be OK, but without the data sheet for the chip I can't say if the substrate diodes will take this or not- unlikely. In any event, it is very bad practice. But don't worry the solution is straight forward. Sorry to say, that putting a capacitor between the chip clock pin and 0V could make things worse, but you were looking in the right area.
(3) The outputs from the chip to the SCRs, and the SCRs themselves also look vulnerable. I'm still considering this area.