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Also,If bit OERR is set, transfers from the RSR register to the RCREG register are inhibited, so it is essential to clear error bit OERR if it is set.
If your receiver stops receiving data, you should check bit OERR in the RSR register if the receiver has been overrun and clear the error by resetting the CREN bit and re-enabling it after purging the FIFO.Overrun error bit (OERR bit) has to be cleared in software. This is done by resetting the receive logic (CREN is cleared and then set).