i'am appologise for sending my assighment here, but i got too many presure for failure to understand the question needed. below is the question. perhaps, sombody could help me by guide or any thing that would open my mind in understanding the problems and finally come out with the solutions.
Question:
Design a sychronous circuit that has a single input variable and a single output variable. the input data are received serially and cause the first output bit to be the same value as the first input bit in the serial string (ie, if x=0, then z=0 and if x=1 then z=1). output z is to change there after only when three consecutive input bits have the same value. For example;-
X 0 0 1 0 0 1 1 1 0 1 1 0 0 0
Z 0 0 0 0 0 0 0 1 1 . . . . .
1) construct the state diagram describing the system using a moore model
2) using conventional method, obtain the circuit implementation of the system
3) using VHDL write a description for implementing the system.
in advance, i thank you for any helps, guide, info, etc.
Question:
Design a sychronous circuit that has a single input variable and a single output variable. the input data are received serially and cause the first output bit to be the same value as the first input bit in the serial string (ie, if x=0, then z=0 and if x=1 then z=1). output z is to change there after only when three consecutive input bits have the same value. For example;-
X 0 0 1 0 0 1 1 1 0 1 1 0 0 0
Z 0 0 0 0 0 0 0 1 1 . . . . .
1) construct the state diagram describing the system using a moore model
2) using conventional method, obtain the circuit implementation of the system
3) using VHDL write a description for implementing the system.
in advance, i thank you for any helps, guide, info, etc.