help in vhdl for loop

please help me with the following coding...

for(j=0; j<10; j++)
{
for(i=0; i<5; i++)
{
A <= D;
A = A+4;
}
A = A + 10;
}


D value changes for every change in A.... it will be given externally..... D will be different for diffent A... how can i implement this in vhdl.... i am using xilinx 6.1 n modelsim to see d output.... also tel me how can i see the out put...

thanks a lot...
with regards...

code

No one writes and give you the ready made code. Instead you write something and check out, refer here if you got doubts. if you dont know the coding better refer to some beginner books,,not here

I am giving hints.try a code yourself and post the MODELSIM outputs.

[label :] [iteration_scheme] loop
{ sequential_statement }
{ next [ label ] [ when condition ] ; }
{ exit [ label ] [ when condition ] ; }
end loop [label];

That is the syntax in loop equatios. try out now

And to view the output in modelsim is pretty simple. I didnt understand where have you got the doubt

for j in 1 to 16 loop -- length = 16

for i in 1 to 8 loop
a <= d;
a <= a+4;
end loop;
a <= a + 16;
end loop;

here a and d are 32 bits length.... this is the code i hav written..... how can i see the output..... plz help...