My first problems is:
Ok i am doing some VHDL code. right now i have 2 VHDL source which is functioning as it suppose. now i like to combine booth, but i dont want combine it in one source file. What i like to do is to create third source file, than when ever i need that function i just call it. for example:
1) ADDER.VHDL
2) MULTIPLIER.VHDL
3) TOP_SOURCE.VHDL
so in top_source.vhdl, if i need adder operation i just call adder.VHDL to perform the operation. if i not misunderstand it will used port mapping to transfer data to subprogram and from sub program. it like subroutine in C or any other programming language.
can somebody show me how to o this or provide me with an example or website that have the solution to the problems.
My second problems is:
how to crate behaviour to do set 1 operation first than followed by set 2 when set 1 program finished. if in C or any other language, instruction executed line by line. but in VHDL it being executed all at the same time. How can i crate a code let say will add 2 number first than subtract with something and all code written in same process under same behaviour. If cannot! what is the best way to do that.
I thank you in advance.
Ok i am doing some VHDL code. right now i have 2 VHDL source which is functioning as it suppose. now i like to combine booth, but i dont want combine it in one source file. What i like to do is to create third source file, than when ever i need that function i just call it. for example:
1) ADDER.VHDL
2) MULTIPLIER.VHDL
3) TOP_SOURCE.VHDL
so in top_source.vhdl, if i need adder operation i just call adder.VHDL to perform the operation. if i not misunderstand it will used port mapping to transfer data to subprogram and from sub program. it like subroutine in C or any other programming language.
can somebody show me how to o this or provide me with an example or website that have the solution to the problems.
My second problems is:
how to crate behaviour to do set 1 operation first than followed by set 2 when set 1 program finished. if in C or any other language, instruction executed line by line. but in VHDL it being executed all at the same time. How can i crate a code let say will add 2 number first than subtract with something and all code written in same process under same behaviour. If cannot! what is the best way to do that.
I thank you in advance.