Peak and Hold Circuit
Hi there, I am trying to build a peak and hold circuit that will capture the peaks of pulses that are about 5μs in duration or shorter. I can only test with 5μs pulses for now so that is what I am starting at. The pulse frequency can range anywhere from 1.1 Hz to 110 kHz. The amplitude also varies and is normally in the 1-50mV range but I am amplifying it using the PSoC so it is about 50mV - 900mV.
The goal is that once the peak is held I send it to an ADC converter internal to a PSoC 3. Once a couple of conversions have taken place and an end of conversion (EOC) trigger happens I will reset my peak and hold circuit using a MOSFET.
Currently this is the system I have in LTSpice:
View attachment 66051
This circuit has a couple problems, first off the peak it holds is higher than the actual peak:
View attachment 66052
(Green = input, Blue = output)
The second problem becomes more of an issue when this simulation becomes hardware. At the output of the first op-amp a second pulse can be seen when MOSFET turns off. In simulation this second pulse doesn't cause an issue, however in the real world this second pulse is larger than the input pulse and thus the peak and hold circuit peaks on that pulse. This is what I mean:
View attachment 66054
(Green = input, Red = Output, Blue = Output from 1st op-amp, Teal = MOSFET Gate input)
Right now my biggest problem is the 2nd one regarding the extra pulse when the MOSFET turns off (opens the connection between drain and source). Does anybody know why this pulse is created and how to get rid of it?