Frequency doubler circuit for variable input square wave?

Sim looks like 25 Hz (10K ohms and .1 uF timing elements) -



And at 200 Hz



Problem areas, output duty cycle, strong T dependence on gate threshold, strong T dependence of
passive values, noise immunity, in short its a crappy way of getting a well designed circuit.

Note using a Schmidt not much help as its thresholds vary all over the map as well. Better off using
a comparator and a reference to get predictable results.

Trimming RC values could get closer to 50% duty cycle, but overall circuit just poor. Not to mention
discharging cap thru internal CMOS structures on power down, known to create hot spots in die
and possible damage. One could add a series R with gate input between it and cap to prevent this,
buts thats tacky.


Regards, Dana.

I do not see any detrimental effects in the simulations.

The duty cycle should not be critical for a tacho, and the most important thing of all is: it works.

KISS principle - there is no point over-designing this that function fine is a simpler form.

Sure, if its a one off, and no need for 50% duty cycle as originally stated, then sort of retracted,
it would do.

Except the one issue with cap discharge has to be taken care of, that is a failure analysis mode
in CMOS, known since 70's. Dependent on how supply is taken down.


Regards, Dana.

In post #18-
Since the input signal frequency is slow, and the output doesn't need to be 50% duty, might be able to replace the R/C components with pairs of inverters (made from a second CD4093B) to provide the delay?

Of course much of this is speculation based on the fact we do not know what the timing requirements
are for the Tach input.

But the myriad of solutions interesting never-the-less.


Regards, Dana.