This circuit is a simple 3 digit counter with a shared segment bus and time-multiplexed 3 digit display.
Your inputs are; negative edge clock (CP0), Latch enable+ (LE) and Reset. You can LE whenever you want, either while it is counting slowly, or quickly once per fixed interval just before you Reset with repetitive readings like a multimeter at a fixed rate. Meanwhile an internal clock scans each digit fast enough so there is no flicker at say 200Hz to 1kHz, 100Hz will be too slow.
Since you have 3 digits, each ON 1/3 of the time, you must drive it with 3x the average desired current for the same brightness. This
can become a challenge to keep the LEDs at display constant brightness for 1 to 7 segments thru the Common side driver.
Digits come in two Common configurations for Anode or Cathode , (CA and CC). The common side is switched on with a constant voltage normally near V+ for CA and near 0V for CC since the Anodes in CA are always positive., and cathodes in CC are always negative to make the diode forward biased.
When using the CMOS counters or decoders, they are usually "positive logic" meaning active high, but the Digit Select outputs are active low on the 14553. The PNP transistors are used as active low current buffers called
emitter followers. the emitter current is controlled by the base current * hFE and load. But hFE can vary widely from 50 to 800 , so there are constraints in design to reduce voltage variation for the common side of the LED. Current limiting and brightness is always controlled on the segment side, so the Common side must be a fairly stable voltage..
The
14511B is a
BCD to 7 segment latch/decoder/driver whose input comes from the 14553's BCD output below.
The
14553B has a 3−digit BCD counter, a 3 digit latch and a 3 digit MUX with a scanner integrated clock to scan each digit with the correct BCD output during Digit Select. (
DS#)
The BCD counters that are cascaded synchronously which means they update from the input clock edge not from preceding outputs, which we call asynchronous counters.
The quad latch at the output of each counter permits storage of any given count. The information is then time division multiplexed, providing one BCD number or digit at a time. Digit select outputs provide display control. Thus one can use a high frequency clock to measure frequency with an accurate Latch Enable interval OR use it to simply count events and always enable thus update the diisplay is as fast as the internal MUX clock in milliseconds.
Brightness control
The 14xxx CMOS types have 300 Ohms internal driver resistance and when all 7 segments are active with say 20mA for large types, each digit might draw up to 140mA thru the transistor, depending on the LED Vf, supply voltage and choice of segment resistor current and any other voltage drops. The transistor must maintain the same voltage out regardless of the number of segments active. Since V output low or VOL is 0V and we consider hFE of 140 for now, then the base current would be 1mA which results in the digit select active low rising to 0.3V with 300 Ohms internal in series. the BC556 cannot handle much more than 140mA without significant voltage drop and the datasheet indicates at 25'C Vbe rises from 0.63 to 0.83V at 140mA. Now the Common Cathodes will be active at 0.3V+0.83=1.1V max and 0+0.63V min. which is a wide range for a 3.6V LiPo cell supply and but they used a 9V source , but perhaps not because using a battery as this current would kill a 9V battery pretty quick.
The given design is not very bright nor very efficient as most of the voltage drop is wasted in resistor heat with approx 12mA/3 average per LED.
It is possible to improve this design to run from a 3.6V LiPo battery which has more current capacity than a 9V alkaline or a standard 5V supply, by choosing more care in selecting the current limiting parts and LED Digit display type.
The Cap across pin 3-4 is a digit scanner clock timer and is explained very well in the data sheet. Like Memory refresh this is a Digit refresh while each digit is driven sequentially. from the latched BCD counter decoder to MUX out.