• Welcome to our site! Electro Tech is an online community (with over 170,000 members) who enjoy talking about and building electronic circuits, projects and gadgets. To participate you need to register. Registration is free. Click here to register now.

EMI and PICs

Status
Not open for further replies.

darkfeffy

New Member
Hi all,
I posted a thread here sometime about my PIC18f2520 which wouldn't work in my H-bridge. The reasons are:
- I left LVP pin unprogrammed. That's why the PIC was picking up noise and modifying part of the program memory.
- Electromag. Interferance (EMI). Even with LVP programmed off, EMI from the H-bridge (with LC filter connected) keeps interfering with the PIC. As a result, output pins occassionally blank out. Anyone know how to prevent EMI from getting to the PIC? Thought of a Faraday cage but made of what? Also thought of locating the filter as far as possible, but I guess there must be a limit to that...
Better still, anyone know of a PIC with high tolerance to EMI?
Thanks
ed
 

dknguyen

Well-Known Member
Most Helpful Member
-Use a ground plane and a guard ring on your PCB with good capacitor decoupling. Also smart PCB layout and routing will make a difference.
-Increase the rise/fall times of your power transistors using gate resistors
-Minimize loop areas and wire/trace lengths, especially for power traces and gate drive traces
-Use snubber circuits on your H-bridge (similar to increasing rise/fall times of the power transistors)

Are you talking about noise travelling through the traces or actually radiated emissions? Because LC filters won't do much against radiated emissions.
 
Last edited:

darkfeffy

New Member
Here are the original schematic capture and the PCB layout. The white traces on PCB layout are the ground.
U wouldn't find the following modifications on the attached diagram (did all these later on breadboard when the PCB wouldn't work):
- a 100uF electrolytic capacitor b/w Vdd and Vss.
- Vss physically separated from rest of circuit(in fact I used a different dc voltage supply for this)
- 2 opto-couplers b/w PIC and IR21844 gate drivers.
- LVP disabled in software.
- 500Hz LC low pass filter.

dknguyen, the filter is meant to eliminate harmonics so the output is pure sine. Seems it generates EMI as well because the PIC is ok when the filter is not connected...
I supplied the H-bridge upto 48Vdc after which the EMI apparently becomes unbearable to the PIC (with LC filter connected to bridge)
I am new to this stuff, so please explain terms like "rings" being used on the PIC, "ground plane" etc...
 

Attachments

dknguyen

Well-Known Member
Most Helpful Member
http://www.ce-mag.com/ce-mag.com/archive/01/03/0103CE_028.html

Practical electronics for inventors - Google Books

EMC at component and PCB level - Google Books

Ground plane is a solid copper area connected to ground underneath the IC. Often it is an entire layer on the PCB and in that case, the ground plane IS ground and whenever devices connect to ground they connect directly to this plane for lowest impedance to ground.

A guard ring is a PCB trace that runs in a ring around the IC, the edges of the PCB, or even individual pins on a device that are extra sensitive to noise. One end of the trace making the ring is connected to ground. Because of this the trace making the ring is NOT a closed loop. If you close the loop you will make an antenna which makes things worse. THe ring shields the IC, pins, or PCB from EMI and contains the EMI being radiated by the IC/pin/PCB. Do not use the guard ring as a short convenient path to connect devices to ground. It should not carry any current and should be a "dead end trace" with one end connected to ground.

Your PCB layout is not so great either. YOu have the power traces running in massive loops around your PCB (actually completely enclosing the PCB in your case) with all the electronics in the middle. Larger loops = more inductance = more noise and voltage spikes. You basically made a giant EMI generator and stuck your electronics in the middle.

Remember current always flows in a loop and the smallest loop is formed by flowing back the same way you came to make a loop of zero. We can't do this in reality but you can make it very close by making it flow the same path on top of the PCB (+V for example), and then returning over the same path on the bottom of the PCB (ground for example). Keep your loops, especially those carrying high frequencies or high currents as small as possible. If you don't have a ground plane and power plane, running your power traces and ground traces on top of each other also minimizes loop area. If you have enough layers you can just make a power plane and a ground plane and connect everything directly to them which does the same thing (lets the current take the shortest possible route making the smallest possible loop). Even if you have just a ground plane with power traces, the return currents in the ground plane will take the shortest path to make the smallest possible loop with the current in the power traces.
 
Last edited:
Status
Not open for further replies.

Latest threads

EE World Online Articles

Loading
Top