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dsPIC ADC->DAC Loopback: Round 2

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New Member
Hey everyone,
I'm back! :) I've picked up a heckuva lot of knowledge from this place, other forums, and my professors since last time... but its not quite there yet...

I am having some difficulty with this circuit.

My input is an iPod who's signal centers around 0V and swings +/-1V.

The ADC, in this example, is set to 12-bit processing. According to the transfer function and when Vref+ - Vref- = 3.3V, the theoretical ranges for conversion are:
0V - bottom
1.65V - midpoint
3.3V - max

My op amp circuit has been verified to give me a signal that operates in that range.

Now, when I load the chip with this signal, I get crickets out of the DAC. Nothing. No signals at all. I realize it is a differential output and, with a scope, I see nothing and with a differential->single-ended op amp circuit, I also get nothing.

I don't understand. My signal should be in range. My code should work correctly. Therefore, my DAC should output something. Right?

Any suggestions? Here is my schematic:



Well-Known Member
Most Helpful Member
It sounds like your oscillator is running much slower than expected. Are you selecting the right speed for the internal oscillator? Can you flash an LED to confirm the speed?

I'm assuming the chip in question has an int osc.



New Member
dougy83: Damn, yeah when I was plugging and prodding around with wires once, I found that pulling MCLR to Vdd seemed to make it work oddly enough (but other parts of my circuit were wacky so, at the time, it didn't look like the perfect solution). I will definitely give this a shot tomorrow!

What about this makes it work? I thought MCLR would reset the program, no?
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Well-Known Member
MCLR is an active-low reset line (and I don't think it's pulled up internally).

So if MCLR is low, then the processor is held in 'reset' state. When it's high, the program can run.


Active Member
Sometimes it's the simplest things :)

Further explanation: MCLR is an active low reset. It also is hit with a high-level voltage (Vpp) during the in circuit serial programming process to blank the chip's memory. In general, MCLR should be tied to Vdd through a 10K resistor and also have a reset switch to pull the pin low. The resistor protects the Vdd lines from overvoltage when applying VPP to MCLR during the ICSP process. The switch is just nice to have if your system hangs when prototyping, but it's not necessary for the chip to work.

ON SOME NEWER DEVICES there is an internal MCLR pull-up, but this is not universal. These devices allow for the MCLR pin to be used as an input pin (cannot be used as an output) when the registers are programmed for it operate that way. I think this prevents using ICSP, but I am not sure.

HTH, and feel free to correct me anyone.
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