If anyone is interested, here is a partial code listing for the Message Generator Initiator. It's job is to simply generate addresses for the ROM so that message data can be transfered to the receive FIFO. To those who have programmed, but not familiar with verilog, you will recognize some of the constructs, as verilog was created from programming languages like FORTRAN, ADA and C. In fact, some simulators translate the verilog code to a C program before assembly and execution.
If anyone wants the code (once it's finished and tested, of course) I might just put it up on my website, rather than pasting it all over this site, as long as I don't run afoul of the site's policy of not allowing advertising. If I give the code away, and don't have advertising on my site, is it still advertising?
Also, how do I wrap the following code in one of those cool code windows, with the slider bars? I'd like to edit this post to do just that, if someone can tell me how.
module msg_init
(clk,
reset,
etx,
address,
read_ena);
input clk;
input reset;
input etx;
output [5:0] address;
output read_ena;
reg [1:0] state, n_state;
reg[5:0] address, n_address;
reg read_end, n_read_ena;
parameter reset = 2'b00;
parameter read = 2'b01;
parameter done = 2'b11;
always @(address or read_ena or state or etx)
n_state <= state;
n_address <= address;
n_read_end <= read_ena;
case (state)
reset:
begin
n_address <= 0;
n_read_end <= 0;
n_state <= read;
end
read:
begin
if(etx) begin
n_address <= address;
n_read_ena <= 0;
n_state <= done;
end
else begin
n_address <= address + 1;
n_read_ena <= 1;
n_state <= read;
end
end
done:
begin
n_address <= address;
n_read_ena <= 0;
n_state <= done;
end
endcase
end //always