Design a circuit for a latch using NAND Gates

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Jaden

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Hello. I'm having trouble with part of this problem I'm working on.

Part of it wants me to "Derive a circuit for the AB latch that has four 2-input NAND gates and 2 inverters". This is where I'm stuck at I have no idea how to do this.

I also wanted to know if I got this right. In the first part it asked for us to make a state table and equation for AB as follows:

A and B = 0, Q = 0
A or B = 1, Q is unchanged
A and B = 1, Q = 1

A B Q+
0 0 0
0 1 Q
1 0 Q
1 1 1

Q+ = BQ + AQ + AB
 
Last edited:

hi,
The Table is incorrect for a NAND gate.
I would suggest you write out the Truth table for an AND gate first , then negate [invert] the output state values of the table to give the NAND gate.
 
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Please reconsider the problem. He is to use NAND, that is Not AND rather than AND Not gates. In spite of common usage they are not the same, especially in class.
 
Since the answer provided is based on the AND NOT gate, he hasn’t been given the correct answer.
 
Gary B said:
Since the answer provided is based on the AND NOT gate, he hasn’t been given the correct answer.
Click to expand...

hi gary,
We dont normally give the answer to homework questions only hints or suggestions.

 
I did not provide an answer, just pointed out the sloppy language. While I don’t believe in giving straight homework answers, I don’t believe in trick questions or leading students astray which I think was starting to happen.
 
Hi,


I assume we are taking NAND to mean the typical logic gate, so that would be c=NOT(AND(a,b)). In other words, an AND gate with the output inverted, not an AND gate with the inputs inverted.
 
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MrAl said:
Hi,


I assume we are taking NAND to mean the typical logic gate, so that would be c=NOT(AND(a,b)). In other words, an AND gate with the output inverted, not an AND gate with the inputs inverted.
Click to expand...

hi Al,
Thats also the way I understand it.

Gary B
I did not provide an answer, just pointed out the sloppy language. While I don’t believe in giving straight homework answers, I don’t believe in trick questions or leading students astray which I think was starting to happen.
Click to expand...

I've been called many things but never sloppy.!
 
It was not my intention to call you anything let alone “sloppy.” I am merely attempting to point out that a Not AND gate is the equivalent of OR Not gate and Not Or gate is the equivalent of And Not gate. Since common usage of NAND is an AND Not gate, I just wanted to make sure that the question asked is the one that was intended.
 
A B Q+
0 0 0=to get that state u can use a NAND gate and then connect the output to an inverter,at 00 NAND gate output is 1 ,inverter will invert it to 0

0 1 Q= simply use the NAND gate
1 0 Q= use NAND gate
1 1 1=use NAND gate and an inverter, at 11 NAND gate output is 0 so inverter will invert it to 1.
ALL THE BEST FOR UR CKT IMPLEMENTATION
 
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