deriving a capacitor's voltage

[Heidi]

Personally, I don't think it is impractical or artificial. It's just a case to look at. If you have a poor capacitor and a poor current source, then you will get fast decay of the offset voltage. If you have very good devices, you will see a much longer time before the decay is noticeable.

I didn't think of that. Thanks!

 

[MrAl]

Hi again,

Ok, then i was able to verify your solution too, assuming your sin(bt) was meant to be sin(wt) of course

BTW i found that it was easier to solve using the Thevenin/Norton current to voltage source transformation, which then turned the circuit into a single voltage source driving a capacitor with a single resistor (Rs+Rc) in series. Either voltage response (Vc or Vc+vRc) is then fairly easy to obtain.


I think the impractical part of driving a cap with a real life sine current source is if there is any DC offset in the source wave the cap charges until it blows up

Any waveshape difference top and bottom can cause an average DC offset too. This kind of thing is a problem in transformer primaries that are driven with PWM intended to have the average shape of a sine wave. Differences in the H bridge transistor voltage drops can cause higher pulses one way than the other. This in turn ratchets the current up so the core moves more toward saturation, and then the peaks of the would-be sine cause annoying audible noise in the transformer.

 

[steveB]

I think the impractical part of driving a cap with a real life sine current source is if there is any DC offset in the source wave the cap charges until it blows up

This is an excellent point. In another recent thread Heidi showed that the modeling software did not like to model an ideal current source with an ideal capacitor. In that thread it was pointed out that a parallel resistor is needed to "make the software happy". This is probably due to the marginal stability of an integrator. So, mathematically, the solution is fine for the ideal case, but in practice or in numerical simulation, a parallel resistor is needed to have a stable circuit. Alternatively, the current source could have a low bandwidth feedback loop that adjusts its DC offset based on the DC offset of the output.

 

[Heidi]

I think the impractical part of driving a cap with a real life sine current source is if there is any DC offset in the source wave the cap charges until it blows up

Hi, MrAl.

Do you mean that if the current source is (5+sin(w*t)) Amperes, for example, then it might blow up the cap before the current reaches 5+1=6 Amperes?

 

[JoeJester]

I tend to think the modeling software is trying to get as real life as possible.

That being said, thete are constraints when working with perfect sources. You can have a femto value of resistance to satisfy the software.....which wouldn't change the answer in most circuits. It is important to know the software.

I am a neophyte but i investigate all errors to resolve the issue.

Some common issues are using initial charges when working with oscillators, however, reworkimg the circuit with different values can be the solution, while maimtaining the specifications, when starting the simulation with zero initial conditions (simulating normal power startup).

Ive had circuits simulate faster by reworking the values. I feel if the simulator cant solve it within the various constraints
It is worthwhile to review.

Im on my phone so i cant remember the constaints. Sometimes resolving to the micro or nano accuracies is outside the realm of expectations. that was an inaccurate statement.

on edit ... back at the computer.

Just to illustrate, here are the transient analysis parameters for both floating nodes and oscillators. You can note the default values in parenthesis ... I typically use just the defaults.

 

[Heidi]

Oops! If current (5+sin(w*t)) Amperes is flowing through a cap, then after a short time T, the charge accumulated on the cap, integral of (5+sin(w*t)) from zero to T, might cause dielectric breakdown and short out that cap.

Now I understand what you meant by

if there is any DC offset in the source wave the cap charges until it blows up

The remaining question is why "a real life sine current source" has a DC offset?

 

[MrAl]

Hello Heidi,

Yes, you figured it out nicely

The integral of a constant K is that constant times t, or K*t which is a ramp, and a ramp increases forever, so if K*t represents the voltage then that voltage builds forever and in the real life circuit something has to give.
The current doesnt even have to be that high either. We dont even need 5 amps or even one amp, because even a small constant current like 1ua still integrates to infinity after enough time has passed. Yes, a 5 amp source will cause this to happen faster, but the 1ua current will still cause the voltage to rise forever.
Of course the secondary effect to consider with the lower current is the parasitic nature of the cap, namely the leakage current, or what we could say is the parallel resistance that seems to appear across the cap terminals. In the case of the cap and parallel resistance, if the current times the resistance does not exceed the voltage rating of the cap, then it wont blow up, but unfortunately there will still be some unwanted DC offset voltage then which may interfere with the normal working of the circuit. So with 1ua and 1Megohm, the max voltage will be 1v, which wont hurt anything. If the leakage is less like say 10Megohms, then the max voltage is 10v, so that's starting to look more troublesome. You get the picture. Of course it also depends on the max voltage capability of the current source, but we wouldnt want to max out the current source either.

Why a real life current source 'can' have a DC offset? Why not ?
It depends highly on how it was generated. In fact it is very very hard to get a circuit with a symmetrical pattern above and below zero to NOT generate a little offset because it is so hard to generate a perfectly (and i mean absolutely perfect) symmetrical waveform above and below zero without placing a cap in series with it (assuming then that the leakage current is acceptable). It would probably be generated with a circuit with transistors, and transistors have voltage drops which are not exact, as well as normal component tolerances which cause individual components to be different even when they are marked the same. This shows up in varies ways, such as around the zero crossing or near the peaks, and remember that even the smallest difference between the waveshape above zero and the waveshape below zero causes a DC offset.

Not all DC offsets will cause a component failure as mentioned above with the parallel resistance. If the resistance can take the current without allowing the voltage to get too high then it's going to survive. It can still mess up the operation of the circuit, but at least the component will not fail.
With capacitors it is the parallel resistance that makes the difference while with inductors it is the series resistance that makes the difference. If the cap's parallel resistance is low enough, it prevents the voltage from rising too high, while if the inductor's series resistance is high enough it prevents the current from rising too high (due to an unwanted DC voltage offset).

If you wanted to see the effect of a non symmetrical sine you could probably integrate a sine with a given amplitude over the positive half cycle, then change the amplitude a little and integrate over the next half cycle, something like that.
A*sin(2*pi*1*t) [0 to 0.5]+B*sin(2*pi*1*t)[0.5 to 1]
which would look like:
(A-B)*sin(2*pi*1*t)[0 to 0.5]
The average value of that depends on A and B, the peak amplitudes of each half cycle.

 

[Heidi]

Hello, MrAl

After studying your reply very carefully, I still have a couple of things I need to be sure of.

Of course the secondary effect to consider with the lower current is the parasitic nature of the cap, namely the leakage current, or what we could say is the parallel resistance that seems to appear across the cap terminals.

Is the "lower current" mentioned the current with low frequency?

If the leakage current for a given cap can be modeled by a resistor Rp, and if a sinusoidal voltage with a DC offset, V0*sin(2*pi*f*t)+Vdc, is across the cap:

What would be the leakage current?
leakage current=(Vdc/10^6)?
Does the leakage current have anything to do with the frequency of the voltage across the cap?

 

[Heidi]

Maybe I should have asked my second question this way:
When including the effect of leakage current, is the linear capacitor model mentioned above applicable to the situation where it is driven either by a DC voltage/current source or by a DC+AC one?

 

[JoeJester]

If anyone is still interested, here are two webpages that discuss the modeling of capacitors.

http://www.ecircuitcenter.com/Circuits/cmodel1/cmodel1.htm

http://www.ecircuitcenter.com/Calc/Cap_Model/CapModelCalc1.html

 

[Heidi]

If you wanted to see the effect of a non symmetrical sine you could probably integrate a sine with a given amplitude over the positive half cycle, then change the amplitude a little and integrate over the next half cycle, something like that.
A*sin(2*pi*1*t) [0 to 0.5]+B*sin(2*pi*1*t)[0.5 to 1]
which would look like:
(A-B)*sin(2*pi*1*t)[0 to 0.5]
The average value of that depends on A and B, the peak amplitudes of each half cycle.

Assume that an ideal capacitor has reached its steady state when a current i(t) which has the pattern
i(t)=A*sin(2*pi*1*t) for (0+n) =< t =< (n+ 0.5),
i(t)=B*sin(2*pi*1*t) for (0.5+n) =< t =< (n+1), n=0,1,2,3...
is flowing through that capacitor for t >= 0.

If A > B, the following integral

represents that for every second, there is an additional charge (A-B) going to be added to the cap, so the cap is very likely to blow up after a finite time has passed.

Is it correct?

 

[Heidi]

If anyone is still interested, here are two webpages that discuss the modeling of capacitors.

http://www.ecircuitcenter.com/Circuits/cmodel1/cmodel1.htm

http://www.ecircuitcenter.com/Calc/Cap_Model/CapModelCalc1.html

Seems like the parallel (resistor-ideal capacitor) model can also be used when driven by AC sources?

 

[MrAl]

Hi again Heidi,

Let me see if i can address your questions from post #28 first.

To begin, when we place a resistor across a capacitor the circuit is still linear. It's just a cap in parallel with a resistor which i am sure you've seen lots of times. The real difference is now we have something that 'short circuits" the cap in a way for current, so that even if the cap charges up there will still be something there to conduct the current. If the current is small, then the voltage can not rise very high. In fact, then it's just Ohm's Law: V=I*R. If the current is only 1ua (aka 'a low current') and the resistance is 1 megohm, then the limiting DC voltage across the cap is 1v. If the current is 10ua, then the limiting DC voltage is 10v, etc. So the parallel resistors helps to partially reduce the effect of the constant part of the current source (the DC part). It doesnt really get rid of it though, it just limits it to an acceptable level. Note here 'acceptable level' depends on the application too of course, as some apps dont like much DC at all, while others can tolerate a little.

BTW the circuit we are really talking about is your circuit from post #28 but with the following changes:
1. The sine voltage source is changed to a sine current source with significant amplitude (considered to be the main signal) in parallel with a DC current source of relatively low level.
2. The DC voltage source is removed and the two terminals where the source was are shorted out.
So basically we have a sine current source in parallel with a DC current source driving a capacitor in parallel with a resistor and the resistor is considered to be the parallel resistance that represents the leakage.
As Steve noted early on, there is also a small series resistance but for now we dont have to include that.
They also go farther sometimes and include a small series inductance, but we dont need that right now either.
They also go farther than that even and start to add the physical effects of length but i think that's beyond our needs for the most part.

So the main function of the parallel resistor is to model the leakage and leakage will help to reduce the effect of a small DC current, or we can add a resistor to help with this too.

As far as the resistor changing the frequency response, it should only affect the amplitude not the sensitivity to frequency, but it could very well affect the frequency sensitivity too if that cap is used in some sort of filter especially an active filter. Of course the Q of any such filter would also be reduced in most cases where the cap is part of the frequency selectivity function.

 

[Heidi]

Hello MrAl,

I would like you to see if I understand your explanations correctly, please.

Here we're talking about the circuit in Fig.1 below.

1. If the leakage current of a capacitor and its effects can be modeled by a resistor in parallel with the cap, then there is nothing special about the leakage current, and the cap can be treated just like an ordinary RC circuit, no matter the excitation is DC, AC , or AC+DC.

when we place a resistor across a capacitor the circuit is still linear.

2. So now we can analyze the circuit in Fig.1 by analyzing the circuits in Fig.2 and Fig.3 separately and adding the results.

3. In steady state, the voltage across the cap in Fig.1 is then a sine wave (with a phase angle) plus a DC offset, and the DC offset can be totally determined by the DC current source and the parallel resistor, that is 1V in this case.

4. If the DC voltage across the cap is undesirable, we can simply add another (much) smaller parallel resistor across the cap to reduce it.

 

[MrAl]

Hi,

Yes that all looks correct. The only caution would be with #4 where we add a resistor, the resistor obviously can not be too small or else it will swamp out the AC source too and that's the one we probably care about most.
We can also remember the old quote, "A capacitor is an open circuit for DC".
The resistor on the other hand affects both the AC and DC as you can see.

 

[Heidi]

The only caution would be with #4 where we add a resistor, the resistor obviously can not be too small or else it will swamp out the AC source too and that's the one we probably care about most.

Oh, yes, thank you very much for reminding me. I forgot that adding an additional parallel resistor may reduce the AC current/voltage through/across the cap too!

Thanks again!

 

[JoeJester]

Heidi,

The leakage in an capacitor should be very small. I remember testing a 10 uF capacitor rated at 25kV for leakage. It was in the microamperes region. The test equipment was a HI-POT, a power supply that was capable of 50 kV. I don't recall the amperage at that level. The parallel resistor should be very high. Naturally, if you wanted to see the effects of a leaky capacitor, lower the shunt resistor value.

Quoted this message by mistake below while correcting it.

 

[JoeJester]

The leakage in an capacitor should be very small. I remember testing a 10 uF capacitor rated at 25kV for leakage. It was in the microamperes region at 25 kV. The test equipment was a HI-POT, a power supply that was capable of 50 kV. I don't recall the amperage at that level. The parallel resistor should be very high. Naturally, if you wanted to see the effects of a leaky capacitor, lower the shunt resistor value.

 

[Heidi]

The leakage in an capacitor should be very small. I remember testing a 10 uF capacitor rated at 25kV for leakage. It was in the microamperes region at 25 kV. The test equipment was a HI-POT, a power supply that was capable of 50 kV. I don't recall the amperage at that level. The parallel resistor should be very high

Interesting.

I asked to myself, "How can I measure the leakage current of a capacitor?"

Here's a possible way I can think of:
We charge a cap with capacitance C and measure its voltage, let this initial voltage be Vo. Then after a period of time T, we measure its voltage again, let it be V1.

What we know now is
v(0)=Vo,
v(T)=V1,
the voltage equation of a cap, v(t)=Vo*exp(-t/RC), and the cap's capacitance C.
What we don't know is the cap's parallel resistance R used to model its leakage.

To find the value of R, we do the following:
v(0)/v(T)
=Vo/(Vo*exp(-T/RC)
=1/exp(-T/RC)
=Vo/V1

exp(-T/RC)=V1/Vo
-T/RC=ln(v1/Vo)
R=1/[(-C/T)*ln(V1/Vo)]

Since the current flowing through a cap is i(t)=C*(dv/dt)=C*(-1/RC)*Vo*exp(-t/RC),
hence the leakage current flowing through R is
-i(t)=(V0/R)*exp((-t/RC)

Assume the cap's initial voltage is 25K V, after a period of time of , say, 5 seconds, its voltage becomes 20K V. With C=10u F, then R=2.24Mega ohms, and the leakage current is 11.16mA at t=0, begins to fall exponentially.

Well, I'm not sure if this method is practical or not because it depends on how accurate we can measure the cap's voltage, and it was assumed that we know its capacitance in advance.
So, anything else I should be aware of?

 

[MrAl]

Hi,

Yes Heidi that sounds like an interesting idea.

I used to have a very very old capacitance/inductance bridge that also had a way to test for leakage current. It only went up to something like 400 volts though and was made for caps that were used in tube amplifiers and maybe radios and stuff like that, not really high voltage sections of CRT TV's and the like. But if you can measure the current with the required voltage then you can use Ohm's Law because the pure part of the cap is out of the picture with DC current, so we are left with just:
R=E/I

Of course sometimes we dont want to connect our sensitive current meter n series with a cap unless we are very careful, so in that case it might work to add a series resistor maybe 1k or something, and then use Ohm's Law to calculate the current:
I=E/R

where R is the sense resistor.

I like the exponential idea too though with e^(-t/RC) or even while charging the cap with 1-e^(-t/RC).