delayed step signal

[aashish11]

Hi,
I am going to make a 3 bit ring counter using 3 7474 D-FFs. It is my habit to first simulate and then actually design, the PSpice capture simulation is as,
**broken link removed**

Now what I want to ask ?

How to generate the P2 signal which is LOW for 2ms and then HIGH (for ever till the supply is on). It is like u(t-2ms) where u(t) is unit step function (=1 for t>0 and =0 for t<0)

Or is there any other way to load 100 in my counter automatically just after turning on my counter.

Using a 555 timer I have to give trigger but I want P2 automatically i.e., as soon as I turn on the main supply the counter starts running 100 should be loaded automatically.

Please reply soon I am in a great need of it.

 

[ericgibbs]

Hi,
I am going to make a 3 bit ring counter using 3 7474 D-FFs. It is my habit to first simulate and then actually design, the PSpice capture simulation is as,
**broken link removed**

Now what I want to ask ?

How to generate the P2 signal which is LOW for 2ms and then HIGH (for ever till the supply is on). It is like u(t-2ms) where u(t) is unit step function (=1 for t>0 and =0 for t<0)

Or is there any other way to load 100 in my counter automatically just after turning on my counter.

Using a 555 timer I have to give trigger but I want P2 automatically i.e., as soon as I turn on the main supply the counter starts running 100 should be loaded automatically.

Please reply soon I am in a great need of it.

hi,
Post the LT spice 'asc' file, with some added notes, we can see better what you are asking for.

 

[ericgibbs]

hi,
Is this what you are asking.?



View attachment 7474cntr1.asc

 

[aashish11]

Great thanks for your reply..............

Post the LT spice 'asc' file, with some added notes, we can see better what you are asking for.

Sir I am not using LT spice I use OrCAD PSpice Demo. There is no .asc (as far as I know)

Is this what you are asking.?https://www.electro-tech-online.com/attachments/7474a-gif.38732/

Yes the same thing how to generate set1 pulse.

In simple words How to generate,
**broken link removed**
by using hardware ?

 

[MikeMl]

Are you asking how to make a "power-up-reset" circuit? A circuit that will generate a Reset pulse to flip-flops every time power is applied?

 

[ericgibbs]

Great thanks for your reply..............


Sir I am not using LT spice I use OrCAD PSpice Demo. There is no .asc (as far as I know)



Yes the same thing how to generate set1 pulse.

In simple words How to generate,
**broken link removed**
by using hardware ?

hi,
Look at this circuit for a hardware solution.
I prefer Option #1, using a schmitt inverter to give fast well defined switching levels.
Note: that F/F's #2 and #3 are also RESET by the SET pulse to F/F #1, so that the states are: 1,0,0

 

[aashish11]

hi,
Look at this circuit for a hardware solution.
I prefer Option #1, using a schmitt inverter to give fast well defined switching levels.
Note: that F/F's #2 and #3 are also RESET by the SET pulse to F/F #1, so that the states are: 1,0,0

Thanks a lot, but unfortunately when I tried to simulate on OrCAD PSpice I got this,
**broken link removed**
What happened I don't know but I could not get this,
**broken link removed**
at the o/p of the schmitt inverter.

Is there any IC that can generate such pulses e.t.c. ?

 

[aashish11]

Are you asking how to make a "power-up-reset" circuit? A circuit that will generate a Reset pulse to flip-flops every time power is applied?

Thanks MikeMl

I am hearing "power-up-reset" circuit for the first time from you, can it generate,
**broken link removed**
My aim is only to load 100 to my counter at power on automatically
i.e., as soon as I power on my ckt. the ring counter should start ringing automatically without first loading 100 in it and then switching on 555 for clock pulse.

 

[MikeMl]

What type of logic are you using 7400? 4000CMOS? etc?

Never mind, I just went and read your first post.

With 7474s, it takes a low to reset, so a 2.2uF from the reset pin(s) to ground, a 10K pull-up to 5V. When power is first applied, the capacitor is discharged, holding the reset pin(s) low. The capacitor charges via the 10K and the current being sourced from the inputs, removing the reset. When the circuit is unpowered, the capacitor discharges through the 10K into the (now low) Vcc line...

 

[ericgibbs]

Thanks a lot, but unfortunately when I tried to simulate on OrCAD PSpice I got this,
**broken link removed**
What happened I don't know but I could not get this,
**broken link removed**
at the o/p of the schmitt inverter.

Is there any IC that can generate such pulses e.t.c. ?

Hi,
Your images are not being displayed.?????
Use the 'Go Advanced' Option and then 'Manage Attachments' to post your images from your PC to the thread.