Delay on high signl only?

[chico]

I was wondering if there is a type of delay circuit that only delays high signals? (5V logic)
As in if the signal went from high to low I wouldn't want a delay.

I am picturing having a forked signal with 1 part leading to a delay but both paths leading to an AND gate.

This seemed like a good approach to me but you guys have more experience.

 

[ronsimpson]

What kind of delay? nS or seconds?
What kind of no delay? 1nS, 10nS, 100nS?

 

[crutschow]

The AND gate approach would work.

Another way to get a one-sided delay is to use an RC (R in series with cap to ground) delay with a diode across the resistor. For a delay on rise only, you would have the anode facing the capacitor. That way the cap would be slow to charge, but fast to discharge through the forward biased diode.

 

[chico]

@ronsimpson: delay of about 10 s, and "no-delay" of <0.5s

@crutschow: i like how simple that is, would you recommend it for use in logic circuits? any special type of diode?
I like to keep my circuits simple and logic gates have many pins.
Anything to look out for? I imagine i would use a pot instead of a resistor to get the timing just right.

 

[ronsimpson]

An RC delay of 10S is a very long time. Even a delay of 0.5s is a long time.
Electronics timer by CD4060
Time delay relays use a circuit like the one above

 

[chico]

Is the issue with a 10s RC circuit the repeatability?
A 1 MΩ and a 10 µf circuit does 23 seconds its ok if its ±a few seconds every time. I have to have a minimum of 10 seconds but I could just use 20s delay and live with the inaccuracy.
Anyways i will probably just use the AND gate method.
I realized that if I were to use the diode+RC circuit i should put a logic gate of some sort around to make a clean noise free signal.

 

[dougy83]

Is the issue with a 10s RC circuit the repeatability?
A 1 MΩ and a 10 µf circuit does 23 seconds its ok if its ±a few seconds every time. I have to have a minimum of 10 seconds but I could just use 20s delay and live with the inaccuracy.

RC will have a small drift due to temperature variations, but won't be +100%.

I realized that if I were to use the diode+RC circuit i should put a logic gate of some sort around to make a clean noise free signal.

You can use any chip with a schmitt trigger input - there'll then e no problem with the slow rising voltage.

 

[chico]

You can use any chip with a schmitt trigger input - there'll then e no problem with the slow rising voltage.

Can I use a "normal" logic gate? i see that there are gates with and without schmitt triggers, I know a schmitt trigger has hysterysis but would a non-schmitt trigger logic gate be noisy around the trigger point?

Also for the time when the cap is discharging do i need to have a resistor in series with the diode or can I just rely on the ESR of the cap?
right now I'm planning to use 13000 Kohm and 1 uf. This gives a 30 s delay which is plenty of buffer. Is that a reasonable ratio or R:C or should I have a higher capacitance and lower resistance?

 

[misterT]

right now I'm planning to use 13000 Kohm and 1 uf. This gives a 30 s delay which is plenty of buffer.

On what voltage level does the logic gate trigger from low to high? With 13000 Kohm and 1 uf the output will reach 63% of the final value in 13 seconds.. that is 3.15 volts if you use 5 volt logic.

 

[ericgibbs]

Can I use a "normal" logic gate? i see that there are gates with and without schmitt triggers, I know a schmitt trigger has hysterysis but would a non-schmitt trigger logic gate be noisy around the trigger point?

When you say 'normal' logic, which logic family type are you currently using.?

eg: CD, TTL etc...

 

[chico]

When you say 'normal' logic, which logic family type are you currently using.?

eg: CD, TTL etc...

I suppose I mean TTL when i say normal. Looking at a TTL AND gate it says if Vcc is 5 V that the Minimum High-level Input Voltage is 0.7xVcc and the maximum Low-level Input Voltage is 0.3xVcc. Which I assume is hysterisis?
Wheras a schmitt-trigger AND gate uses has high going V+ and low going V- which is thier hysterisis.

So do i need to use schmitt gate to avoid noise around the time of switching to a high output?
I see what you are saying MisterT I will adjust my RC calculation but can I have high a high resistance compared to a low capacitance?
Do i need a resistor in series with the capacitor discharge diode or will the capacitor have enough ESR to keep the diode from exploding?

 

[ericgibbs]

hi,
Using TTL makes the use of high resistor values and long timing periods very difficult to achieve.

Look at this link for the switching levels of the different types.
Logic Voltage Thresholds for TTL, CMOS, LVCMOS, and GTLP IC families

 

[dougy83]

it says if Vcc is 5 V that the Minimum High-level Input Voltage is 0.7xVcc and the maximum Low-level Input Voltage is 0.3xVcc. Which I assume is hysterisis?

That's not hysteresis, it's the limits for a known output state; between those limits the output could potentially be anything. The device you linked to is a CMOS device - if this is your 'normal', then there's no problem (ie the leakage is tiny) with connecting the RC to the schmitt trigger input.

For 0 - 66% in 30 seconds (for 66%, T = 1.1RC) you could use R=2M7, C=10uF. As for the diode series resistance, you could quite happily use a 1k resistor; without the resistor, the diode wont explode but the high discharge current may create some ground bounce which may or may no be a problem in your circuit.

 

[unclejed613]

"back in the day" there was a circuit called a "nosebiter" delay. basically it was a current source/cap time constant and a comparator, and an AND gate. the charging time of the cap was adjustable by adjusting the current source. if the input voltage went low before the output went high, the cap was reset. the circuit got it's name from the linear charging ramp across the cap. another (better) name for the circuit is a Leading Edge Delay, and you won't find "nosebiter" in any electronic context with a google search.
a simple leading edge delay using a resistor, cap and a schmitt AND gate can be found here https://www.electro-tech-online.com/custompdfs/2011/04/AND8408-DPDF.pdf

 

[chico]

hi,
Using TTL makes the use of high resistor values and long timing periods very difficult to achieve.

Look at this link for the switching levels of the different types.
Logic Voltage Thresholds for TTL, CMOS, LVCMOS, and GTLP IC families

So you are saying that I shouldnt mix different types of logic correct? how do i know what type i have? This for instance doesnt seem to say.

Also when you say that "Using TTL makes the use of high resistor values and long timing periods very difficult to achieve." you mean that because i have to reach 3.7V to switch a CMOS chip and that is in the low slope region of an RC circuit that it will be very innacurrate? But if i use a schmitt trigger device i will be ok.

do i need to worry about getting enough current though a 20 Mohm resistor as dougy suggests in order to switch the gate?

 

[ericgibbs]

hi,
Tell us the IC types/numbers you are using and we will know if they are TTL or CMOS or whatever.

When you look at that link chart you can see that the voltage margins for a TTL input high/low are about 2Vhigh to 0.8Vlow.

 

[chico]

hi,
Tell us the IC types/numbers you are using and we will know if they are TTL or CMOS or whatever.

When you look at that link chart you can see that the voltage margins for a TTL input high/low are about 2Vhigh to 0.8Vlow.

ahh so the part number can tell you what the type is, like 74S is industrial temperatues with a schmitt trigger, neat
EDIT: oops never mind its a schottky not a schmitt

 

[ericgibbs]

ahh so the part number can tell you what the type is, like 74S is industrial temperatues with a schmitt trigger, neat
EDIT: oops never mind its a schottky not a schmitt

hi,
Look here.
7400 series - Wikipedia, the free encyclopedia

 

[chico]

For closure on this thread i have posted my final schematic here.