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Delay/enable circuit for synchronous FET controllers


Well-Known Member
The attached is a circuit which disables a synchronous FET controller whenever the power supply loading goes below ~30%.
This is needed to avoid reversing current in the output inductor, which then causes overvoltages when the synch FET goes OFF.
The circuit also re-enables the controller when loading goes >30%...but does this after a delay of some 1 second or so.
Please can you see any opportunities for reducing component count?

(LTspice and jpeg attached)


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Well-Known Member
Most Helpful Member
Your huge, spread-out schematic with diagonal wires and jogs, is difficult to read.
If you tighten it up and remove the diagonals and jog, I'll take a look.


Well-Known Member
OK Thankyou for offering to have a look.
Its straightened up as in the attached if you wish to see it.


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Well-Known Member
Most Helpful Member
Its straightened up as in the attached if you wish to see it.
But you didn't reduce the size.
It is still way to spread out to see on my screen (for example part designations are unreadable when I look at the whole schematic).
(You must be using a very large screen.)
You need to make the schematic much smaller by moving the parts close together, and reduce the huge font size of all the lettering back to the default, if you want me to be able to read it.


Well-Known Member
Most Helpful Member
OK, thanks, please find attached in PDF
That is just a pdf of your huge schematic which I still cannot read.
You need to reduce the size of the .asc drawing by moving all the elements close together and reduce the font size of all the comments to their default size as I asked.


Well-Known Member
Thanks, here is the background on the above circuit....(below the starred line below)

Sorry to have bothered you with this.......this circuit is being offered as a donation to those who have an interest in using it......which means.....anybody who uses synchronous rectifier fets with bridges/forwards.

To be honest, if you are not interested in the useage of this circuit, then i have to confess, it would not be worth your while to "reduce" it, and i would not like you to waste your time with it.....the circuit is a donation to anybody who wants to use it.....they, of their own volition, may then wish to reduce it......whether of course they wish to post any reduction here is up to them....


The question encompass's one of the last "great untruths" of the SMPS world.

That is, that there is in fact no satisfactory way of avoiding reversal of current in synchronous Bridge/Forward converters when they go into light load.
Most synch rect FET driver App Notes and datasheets will tell you that there is...but its a lie.!
The reversal of this inductive current , is often followed by a switching off of the synch FET, and resultant overvoltage spike, (due to broken inductive current) and large losses in TVS's / snubbers etc. (as shown in sim attached in LTspice)

...So there are no ways round this.....well that is, other than disabling the synchronous FETs when the converter goes into light load.
The other way is to have a controller which always switches, so that the current reversal in light load is always limited........and at no_load the output inductor current just shuttles back and forth, with an average of zero Amps....however, there are no offtheshelf controllers which do this with sych'd have to make your own out of a micro

All offtheshelf synch FET drivers try and sense the reversing current, and then turn off the synch FET after its been sensed...but this is too late...because its already happened by then.
Also, the sense resistors used are very low value, and the signal from them is so small it gets drowned out by one ends up settling for more reversed current than one would like.

So..... i find the standard offtheshelf sync rect drivers leave one open to overvoltage spikes due to the SMPS going into light load suddenly......and then the output inductor current reversing and going the "wrong way" back through the sync rect FET....then the sync rect FET turns off...and the output inductor current has been suddenly broken (and now has nowhere to go)....and thus an overvoltage spike results.....the attached LTspice simulation shows the situation happening at the 2ms point.
(if you change it and make the 1e20R resistors equal to 0.1R (or less), then the effect is mitigated.)

The extra “mitigation circuitry” is not usually tolerated by most project managers….because they say that the offtheshelf solutions must work…otherwise they wouldnt be on the market……but the offtheshelf ones only detect current reversing through the sync rect fet after its started happening…..which is too late really. The offtheshelfer’s also usually detect current reversing through the sync rect fet by “Looking” at the voltage across the rds(on) of the sync rect fet……and AYK this is not a fixed voltage because of rds(on) variation with temperature.

So really, chunky TVS's end up being needed across sync rect fets......or even RCD Clamps.

Most offtheshelf sync rect fet controllers are pretty dreadful things…..and many of them (their datasheets) are honest enough to say how bad the situation of detecting reverse current through the sync rect is…and offer you a way to mitigate noise here by putting in your own compensatory "stray" inductor, to mitigate the effect of stray inductance of eg the TO220 legs, etc.

Here is the NCP4303 sync rect controller shows the "compensatory inductor" that is needed.
It obviosuly has to be "tuned" in value to your PCB layout "strays" etc.
Also, the Current doubler rectifier, with its two output inductors, and single txformer secondary, is the best topology by far for sync rects, because even if the sync rect fet turns off whilst conducting reverse current, there is still some path for the output inductor current to go.

Truly , you should not be running synch FETs (with forwards or bridges) unless you either ..
1....keep switching down to no_load so your inductor current just harmlessly oscillates back and forth when in no_load or light_load
2.....disable your synch rects in light load (which is what the "donation" circuit of the top post does)
3....Literally put a schottky in series with the output inductor, so its current cannot reverse.

...if you do not do either of these things...then you are operating a dodgy SMPS...but you may be getting away with it, because your SMPS is usually loaded above the level where this problem happens (ie just above that point where the output inductor current goes discontinuous) .....or it spends a lot of time in no_load, or very light load, where the controller will then actually disable the synch rects by itself.
Attached please find the circuit needed with all bridge/forward synchronous FET controllers/drivers.
No Sync FET Controller App Note will ever tell you about this....

Very many power supplies always operate at or above 30% load virtually all the time, so they never see the "reverse current nightmare" of synchronous FETs the vendors just hope you're in that bracket....
But really , you need the attached circuit (LTspice and jpeg attached)
It simply shuts off the synch FET driver when the load goes below 30% of max.
It shuts it off straight away....but waits a second or so before enabling the synch FETs when the load goes above 30%

As discussed, the only other way round this, is to use the stray inductance discussed in the NCP4306/3 datasheets.......but good luck to you if you start tiddling about with will take you ages to tune and it wont be tuned for all cases of transient etc....and when you change the FETs , the added stray inductance will need to be changed again.......basically, your company will need to ship you with the product, so you are there to tiddle the added stray inductance about so as to keep fixing it.

.....Its noteable that this "added stray inductor fix" for synch FET controllers was never seen until many years of sales of synch FET controllers...then the failure rate was so high that the semico industries had to 'fess up about it.........millions of tons of scrap power supplies laying waste due to the "forced silence" over this problem.

...Of course , there is another way to fix the rev current nightmare of synch FET controllers...and that's to add enormous snubber/clamp network.....but that isnt the way to go here.

What you mustn't do, is be like most engineers, and just pretend the problem doesnt happen....and rely on the fact that above 30% loading , your safe anyway.....and in the other regions, the FETs will last out a bit of time before they go pop....and then you can just put it down to a "weak batch of FETs".

So anyway..please find the synch FET delayed_enabler/disabler circuit as attached..(its in the top post).....any suggestions for reducing the component count much appreciated?


Please respond if you want the sims referred to above, and i will donate them to you.
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Well-Known Member
Most Helpful Member
To be honest, if you are not interested in the useage of this circuit, then i have to confess, it would not be worth your while to "reduce" it
Well you originally asked if there might be a way to reduce component count, but if you don't really have an interest in that, and you can't be bothered to reduce the size of the schematic, then I will just ignore any further posts on this subject.


Well-Known Member
OK, Thankyou, the main thing is, a great many will benefit from the shown circuit.
Ill have a shout at reducing it myself after ive done this order list.....and will post my reduction here.


Well-Known Member
Though never mind, as soon, the circuit of the top post will be turned into a silicon chip module, and will be sold throughout the world in the Kazillions.......just look what it totally alleviates the dreadful problem of reverse inductor current based overvoltage in synchronous rectifiers of bridges and forwards.........(not Bucks...because the overvoltage just goes back through the buck top fet diode in that case).

And seriously, if anyone thinks that that alternative method with the added tuned "stray" inductor is the way forward.....then yes, as long as you handcuff the engineer and ship them with the product so they can re-tune it, when the need arises......and you can handcuff them to the bench so they spend the months tuning that stray for all transient etc conditions.

Feast your mincers on that top post scm.


Well-Known Member
It seems to me that, following the current monitor and Schmitt trigger, a digital delay would be simpler and cheaper than the analog delay if you want to integrate (in chip form) this function.


Well-Known Member
Most Helpful Member
Yes.....but I have to blow up with ctrl++
That's my point.
If the schematic was laid out in proper fashion with the elements close together and with properly sized fonts, you wouldn't have to blow it up and scroll around the schematic to read the information.

I like neat, compact, professional looking schematics.
If you don't care about that, that's fine with me.
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