D flip flop

[Parth86]

I am confused on following topics
1) synchronous set
2) synchronous rest
3) synchronous set/reset with positive edge clock

anyone tell me these all are D flip flop or the function of D flip flop

 

[JimW]

It really depends on if you are asking about a particular IC, or just asking in general. But the simple answer is: no. The D flip flop that you buy in a particular package may (or may not) have Set and Reset functions. But what defines it as D flip flop is that the data present on the Data input pin is transferred to the output of the flip flop when the clock line transitions from inactive to active (i.e. low to high for a rising edge flip flop). The Set and Reset functions operate independently of the state of the data present on the Data input line.

But all three questions are generally never done. Most all Set and Reset functions in commercial ICs are asynchronous. Having synchronous Set and Reset functions can cause conflicts with the synchronous Data transfer.

JimW

 

[crutschow]

A JK type FF can be considered to have a synchronous set (the J input) and a synchronous reset (the K input). If both the J and K inputs are held high then the FF will toggle states at the clock edge (if that's what you mean by question 3).

As JimW noted, the Set and Reset (or Set and Clear) are typically separate functions that are asynchronous.

Which edge of the clock the FF responds to depends upon the design of the particular FF you are using. I believe most CD4000 series FF's operate on the positive edge but some TTL series FF's operate on the negative edge.

 

[Mike odom]

Most all Set and Reset functions in commercial ICs are asynchronous. Having synchronous Set and Reset functions can cause conflicts with the synchronous Data transfer.

JimW

Jim, just the opposite. Most early f/f's had synchronous set/ reset: think of a counter. When the output hit 15, and the carry bit outputs and is fed back into the reset, you don't want the f/f restting until the next clock pulse, or it would be a divide by 15, not divide by 16.

Most logic f/f in use separately have async set/reset, as the D is very popular.