When adding a label to a node (wire) in LTSpice, you can just give it a name like "FOO", or if the label lands on the end of wire stub, you can optionally make it a "connector" of type Input, Output, or Bi-Directional. Note that named nodes have a special significance: two nodes with the same name NOT connected by a wire ARE connected electrically across a page, or hierarchically, in a multilevel hierarchical schematic, provided that it matches a PIN name on the hierarchical symbol.
i am trying to create a common source and using net list to creat vdd and vout, but i couldnt get the vout simulation. I tried using voltage source for vdd, the result of vout is still the same. Any idea?
Sorry for the late reply...i got it already.
I would like to know of any informative link that i can learn more about small signal analysis.
Example: I have got the attached doc and how do i draw the small signal analysis inorder to find the Vout/Vin?
This has nothing to do with LTSpice. You are asking how to solve two equations (at the operating point, Id of PMos = Id of NMos) in two unknowns (Id and Vout) as a function of Vdd, Vbias and Vin.
This has nothing to do with LTSpice. You are asking how to solve two equations (at the operating point, Id of PMos = Id of NMos) in two unknowns (Id and Vout) as a function of Vdd, Vbias and Vin.
Sorry. I didnt post my question correctly.
Earlier i was asking about the LT spice, but i managed to get it. and the question i am asking above is on hand on calculation. Sorry for the confusion. Thanks.