CPU and memory interfacing

[electronicslearner77]

Hi All,

In general Microcontroller will be interfaced with external memories like Flash and RAM, but the speeds of memory and CPU are different how do we match the speeds? Do I need to always check the speeds of the memory and CPU before interfacing? Does the CPU performance reduces because of memory speeds? How to avoid this?

Thanks in advance,
Regards,
Satya

 

[phalanx]

There is no definitive answer to your question since there are so many different combinations of microcontrollers and memory. As the engineer/designer, it's your responsibility to look at and understand the datasheets of the components in your system so you can at least ask case specific questions.

Generally memory isn't very flexible in terms of timing so you will have to structure the code in your microcontroller to handle it. Your microcontroller may or may not have hardware to support some types of memory which is another factor you must consider.

You ALWAYS have to check speeds before you interface any component.

 

[MrAl]

Hello,


To add to this thread a little...

When you interface serial ROM or RAM into your system you go by the max clock speed of the I/O allowed by the memory. But if you interface a CPU to memory using the address lines then you have to insert wait states into the instruction stream so that the CPU gives the memory enough time to have stable data on the data buss. If the memory is 10ns and the CPU instruction time is 5ns then you have to wait two or more instruction times before the data is available on the buss. This might mean repeating the same instruction two or three times that fetches the data. The modern computer uses wait states where is waits for the required time of the memory.
But as the previous post points out, you have to check the timing on the data sheet of the memory to find out the delay after an address has been put out on the address lines before the data is considered stable.


You might want to mention what kind of memory you are using, and if you are using a CPU or a microcontroller.

 

[electronicslearner77]

Hi all,

Thank you very much for the replies. I am using a microcontroller, this is a general question i am trying to figure out that so much research is done to increase the speed of the CPU, but memory is still at the same speed then it does not solve the purpose by increasing the speed of the CPU. Just I wanted to understand this? I hope research is also done to increase the speed of the memory. I will be able surely asking a definite question when i start the project, which i will start very soon.

Thanks and regards,
Satya

 

[WTP Pepper]

Many EEPROM/FLASH chips have a way to tell if they are ready by reading certain bits of a databus following a write/erase. Some have a hardware output e.g K9 series of SAMSUNG FLASH devices have an open drain signal called BUSY.

In Hardvard architecture it's common to assume your RAM and ROM will operate far faster than the fetch and execute cycle of the CPU. However even the Z80 old time piece has a /WAIT signal when this is not the case.

 

[electronicslearner77]

Many EEPROM/FLASH chips have a way to tell if they are ready by reading certain bits of a databus following a write/erase. .

I have small doubt in this EEPROM/FLASH are memory devices they do not have intelligence like microcontroller, then how they will be able to say that they are ready? Please help me to understand this.

thanks and regards,
satya

 

[ronsimpson]

One flash part I used has a long write time. (short read time) If you write to the flash and read back too fast you get the inverse of the data until the memory write is completed. Then you can read back the true data.

One option is to write slowly. (2mS) OR Write and then read back that location until the data is true. This takes less than 1mS average.

 

[phalanx]

I have small doubt in this EEPROM/FLASH are memory devices they do not have intelligence like microcontroller, then how they will be able to say that they are ready? Please help me to understand this.

This is when you have to pay attention to the worse case timings in the datasheet. The datasheet will either provide you with the worst case timings that still guarantee operation or they will give you enough information to figure it out on your own. You then write your code to meet these timing values and you will be golden. If you don't trust the timing data in the datasheet, you can simply read back the contents of the memory you just wrote and verify that it is correct. If it isn't, you can have your code adjust the timing accordingly.

 

[WTP Pepper]

I have small doubt in this EEPROM/FLASH are memory devices they do not have intelligence like microcontroller, then how they will be able to say that they are ready? Please help me to understand this.

thanks and regards,
satya

Bear with me on this. They do have the intelligence to determine when their RAM buffers are written to FLASH successfully using the R/B flag or the repeat toggling of bit 6. Look up the data sheet for a K9HCG FLASH device. Other than my explanation I cannot help further.

 

[kubeek]

... so much research is done to increase the speed of the CPU, but memory is still at the same speed then it does not solve the purpose by increasing the speed of the CPU. Just I wanted to understand this? I hope research is also done to increase the speed of the memory...

That is why fast cpu's have two or three stages of cache memory, which is faster than dram, and which buffers the most used or most recently used data, there are different alogrithms deciding what stays in the cache memory.

 

[WTP Pepper]

View attachment 67104

Bear with me on this. They do have the intelligence to determine when their RAM buffers are written to FLASH successfully using the R/B flag or the repeat toggling of bit 6. Look up the data sheet for a K9HCG FLASH device. Other than my explanation I cannot help further.