Constant current circuit

[gjoo]

Can someone explain how the constant current circuit works. How the two op amps interact with each other and with the microcontroller?

 

[rjenkinsgb]

R14 is the current sense resistor. Whatever current passes through the circuit causes a proportional voltage drop across that.

The lower opamp just buffers that voltage and feeds it to the MCU for monitoring.

The upper opamp compares it to the voltage from the MCU DAC out, and controls Q1 gate to keep the voltage across R14 matching the DAC voltage.

The opamp gain is likely around 100,000 so the slightest difference between the voltage at its inputs causes a significant change in its output voltage / the FET gate voltage, keeping the two matching so keeping the current to whatever value the MCU sets by the DAC voltage.

It's a very common circuit configuration, eg. these are all similar in principle:

 

[gjoo]

Sorry for the late response, I understand it now, but why is r9 necessary?

 

[rjenkinsgb]

I'd guess that R9 & C4 slow the opamp feedback response slightly, to stop the overall circuit oscillating?

The power FET may have quite a high gate capacitance, which limits the rate of change with just an opamp feeding it.

With any power control type circuit with negative feedback, If the response of the power side is slow and can "overshoot" for any reason, the control side needs slowing to match, otherwise the overshoots can be over-compensated for leading to the whole system hunting or oscillating.

 

[gjoo]

That makes sense, but why such a large resistor value?

 

[rjenkinsgb]

10K is not particularly high?

To get the same time constant with 1K resistor would require a 1uF cap, probably physically larger and more costly.

 

[gjoo]

Got it. Thanks for all the help.

 

[danadak]

The 10K is essentially grounded at one end. So fdbk from OpAmp output
back to input is essentially a differentiator, high pass, providing phase "lift" in the
loop. Helping to offset lag caused by OpAmps internal comp, lag produced by
Miller and OpAmp Zout (which in analysis is inductive), and stray C's external.
Hence improving phase margin.


Regards, Dana.

 

[rjenkinsgb]

So fdbk from OpAmp output
back to input is essentially a differentiator

???

A capacitor from output to inverting input forms an integrator.

Op amp integrator - Wikipedia

en.wikipedia.org

 

[AnalogKid]

The power FET may have quite a high gate capacitance, which limits the rate of change with just an opamp feeding it.

Especially with R5 in place. This is a common mistake when an inexperienced designer uses a power MOSFET in a linear circuit, having seen them only or mostly in switching power circuits.

In a switching power supply, lead and pcb trace inductance and gate capacitance can form an LC circuit that rings after a fast edge goes through it. Power MOSFET gates are driven with a very fast, high-current square wave to overpower the gate capacitance. This forces the FET to go from completely "on" (fully enhanced) to completely off very quickly, reducing the amount of time it spends in its linear region where it dissipates wasted heat. It's all about efficiency.

R5 and the gate capacitance form a single-stage R-C lowpass filter. This limits the gate capacitor voltage rate of change, removing or decreasing the high frequency harmonics from the voltage edge energy spectrum, greatly reducing the ringing waveform amplitude. Without it, a power stage switching at 50 kHz can ring so badly at 250 MHz that it fails RF noise compliance testing.

For example, a gate capacitance of 1 nF (not a particularly large value) with a 100 ohm resistor is a corner frequency of 1.6 MHz. This is 5 ocatves above a switching frequency of 50 kHz, and has no visible effect on the driving waveform. BUT - At 160 MHz, the harmonic attenuation is 40 dB. So how easy is it for this problem to occur? Very. The inductance needed to resonate with a 1 nF capacitor at 160 MHz is only 1 nH. That's not much.

The existence of R5 came about for a reason, but that reason is being lost. In a linear circuit such as a CC source, it does zero good and can complicate things.

ak

 

[danadak]

@rjenkinsgb

I dont know feedback path sure looks like a HPF, differentiator to me :

Regards, Dana.

 

[gjoo]

Should r5 be eliminated?

 

[rjenkinsgb]

feedback path sure looks like a HPF, differentiator to me

But generally, putting a filter in the negative feedback path of an opamp reverses its function in the overall opamp stage?

eg. A high pass in the negative feedback gives the stage a low-pass function.

A differentiator (high pass) in the feedback makes the stage a low-pass, or with no resistive feedback, a pure integrator with the output ramping at a rate proportional to the input current.

That circuit uses the positive input as well, which adds an controlled offset - but it's still an integrator, ramping either way until any error is cancelled.


It's effectively giving unlimited DC gain, but slowed response to avoid oscillation.
A common part of many "servo loop" type designs.

A PID less the P and D, in that case?

 

[AnalogKid]

A common part of many "servo loop" type designs.

Used in many "capacitor-less" audio preamps and power amps where coupling capacitors are considered evil.

ak

 

[danadak]

Should r5 be eliminated?

No, that "effectively", decouples the input and miller C from loading the
OpAmp output and making stability much more of a challenge. And it
helps to de-Q any L in the signal path, reducing or eliminating gate circuit
oscillation.

And effects EMI issues.

rjenkinsgb discussed all the above earlier.​

You should use a scope, and adjust its size in prototype if you find too much ringing
in the gate drive.

An ap note that is somewhat related :

https://toshiba.semicon-storage.com/info/application_note_en_20180726_AKX00068.pdf?did=59460

https://www.ti.com/lit/ml/slua618a/slua618a.pdf?ts=1690717577780&ref_url=https%253A%252F%252Fwww.google.com%252F

Regards, Dana.

 

[AnalogKid]

No, that "effectively", decouples the input and miller C from loading the
OpAmp output and making stability much more of a challenge.

The FET's "Input Capacitance" is only 675 pF. I have not looked up the opamp, but it would have to be an especially delicate little flower not to be able to drive that successfully.

And it helps to de-Q any L in the signal path, reducing or eliminating gate circuit
oscillation.

As above, that type of oscillation in this type of circuit is not an issue. I won't say it's impossible, but it would be rare. And, there are no EMI issues.

ak

 

[danadak]

@AnalogKid

The FET's "Input Capacitance" is only 675 pF. I have not looked up the opamp, but it would have to be an especially delicate little flower not to be able to drive that successfully.

Phase margin of this OpAmp, in orig post, spectarily poor. and lest we forget
we have Miller involved so the 675 pF just a fraction of the problem :

As above, that type of oscillation in this type of circuit is not an issue. I won't say it's impossible, but it would be rare. And, there are no EMI issues.

Page 4 :

https://www.st.com/content/ccc/reso...df/jcr:content/translations/en.CD00003900.pdf

But to your point this OpAmp has very poor slew rate, so that may mitigate concern.. But I would
confirm switching with a scope looking at gate....


Regards, Dana.

 

[AnalogKid]

Your link, front page, section 2.1, first sentence:

"Power MOSFETs and IGBTs are simply voltage driven switches, "

That is the focus of that app note, and every waveform image shows switching waveforms.

That app note does not apply to this circuit. Again, this is a linear circuit. Other than a possible turn-on or initial value transient, there is no (intentional) switching going on anywhere. There are no nanosecond or microsecond edges being applied to anything; especially, as you pointed out, by that opamp.

The load capacitance sensitivity is disappointing, and R5 should be left in for that, but not for high-frequency ringing that basically is a transient effect.

ak

 

[danadak]

Load step can turn that linear circuit into a switching environment,
especially when it encounters slew rate limiting its no longer a linear circuit.
And a poor switching circuit to boot.

Other than a possible turn-on or initial value transient, there is no (intentional) switching going on anywhere.

Cant agree more, exactly right. The goal here is to prevent unintended switching.

Linear circuits are quite capable of turning into switching circuits when
phase margin disappears.

Ap note on switching simply adds to the discussion, eg. the comments on Miller,
a linear phenomena. The comments on dV/dT, all linear derivations......

Regards, Dana.