Constant amplitude output circuit design?

[ClydeCrashKop]

Does anyone have examples for a simple zero-crossing detector?

 

[pavjayt]

Hi,

The best you can do is probably to amplify a little bit with an op amp, then use a zero crossing detector.
You want little or no phase shift in the amplifier, and detect as close to zero as possible so you do not introduce a varying phase shift with amplitude.

That's exactly what I am noticing while trying out comparators & amplifiers, the phase shift introduced by varying amplitude. This is the reason why I inclined to go back to PLL route. But I would like to use the TTL produced by the driver while at the same time using sine as reference.

 

[MrAl]

Hi again,

Well detecting the zero crossing close to zero should help. For example, a comparator powered with plus and minus 10 volts can be used by grounding one input. When the sine goes through zero, the output will change state. It will be as close to zero as the input offset spec of the comparator, which is typically 2 or 3mv.

It has to be close to zero because when the sine amplitude varies that means if the threshold is at some offset like 0.5v, that voltage occurs at different points in time for different amplitudes, or to put it another way, that point occurs at a different phase for a different amplitude.
For example, with a 0.5v threshold and a 1v peak sine, the trip point occurs at 30 degrees, but with an amplitude of 2v peak, the trip point occurs at about 14.5 degrees.

 

[pavjayt]

Hi again,

Well detecting the zero crossing close to zero should help. For example, a comparator powered with plus and minus 10 volts can be used by grounding one input. When the sine goes through zero, the output will change state. It will be as close to zero as the input offset spec of the comparator, which is typically 2 or 3mv.

It has to be close to zero because when the sine amplitude varies that means if the threshold is at some offset like 0.5v, that voltage occurs at different points in time for different amplitudes, or to put it another way, that point occurs at a different phase for a different amplitude.
For example, with a 0.5v threshold and a 1v peak sine, the trip point occurs at 30 degrees, but with an amplitude of 2v peak, the trip point occurs at about 14.5 degrees.

This is the exact behavior I am noticing with my setup. As the amplitude changes the phase of the output square wave changes relative to input sine.

There got to be some way to resolve this problem and get a very stable square wave out of a sine way that has above zero amplitude. This can be done by detecting zero crossing as close to zero as possible as you mentioned, but how can we achieve this?

More ideas?

 

[MrAl]

Hi,

Use a comparator powered by plus and minus voltages, then ground one input of the comparator and use the other to detect the zero crossing (sine input). The output changes state when the input sine goes through zero, with pretty good accuracy.

 

[pavjayt]

Hi,

Use a comparator powered by plus and minus voltages, then ground one input of the comparator and use the other to detect the zero crossing (sine input). The output changes state when the input sine goes through zero, with pretty good accuracy.

I am gonna try this way and see how accurate it would be. How about AD790? Dual ±15V supply and Input voltage range. There are 3 part#s for this IC which differ in their Input Characteristics, which one would you recommend?

thanks

 

[ronsimpson]

The K/B part has the best input offset numbers but the price will be high.

 

[pavjayt]

The K/B part has the best input offset numbers but the price will be high.

K variant is not available anywhere at online retailers, so I got J variant which is available everywhere. Will see how it works.

 

[dr pepper]

A cmso 40106 might do the trick, you can bias the inverter with a pot so that its close to switching point.

 

[pavjayt]

A cmso 40106 might do the trick, you can bias the inverter with a pot so that its close to switching point.

Do you have a part# in mind that you can share?

 

[crutschow]

The problem could be noise on the signal which would cause the zero crossing point to jitter. That's difficult to eliminate. You may need a PLL, such as the CD4046 to minimize the jitter, as you suggested.

 

[pavjayt]

The problem could be noise on the signal which would cause the zero crossing point to jitter. That's difficult to eliminate. You may need a PLL, such as the CD4046 to minimize the jitter, as you suggested.

You may be totally true, I was just thinking about the noise in the sine wave itself that might give rise to the 1us jitter even on the TTL from the AGC circuit of the source driver. Now the question is about an efficient schematic using a 4046 with sine wave or can I still use the TTL from the AGC and get it tuned even better to reduce the jitter? I am currently using the TTL with a 4046 on the schematic that I had above and it still has jitter in it. I am wondering if I can ever get the PLL output to be stable/close to the input sine wave (which is what I am looking for).

 

[MrAl]

Hi,

How stable is the frequency which i think you said was around 16kHz?

 

[pavjayt]

Hi,

How stable is the frequency which i think you said was around 16kHz?

That's a really good question. Well when I view on it on my Oscilloscope, and triggering on itself, the frequency measurement is hovering exactly between 15.38kHz - 15.43kHz with an occasional reading of 15.41kHz with a jitter of 200ns in the TTL that it is generating.

 

[ronv]

If it is offset the AD790 will be better, but you may see multiple pulses at the zero crossing from noise. But certainly worth a try. Is it better with the high amplitude signal?

 

[pavjayt]

If it is offset the AD790 will be better, but you may see multiple pulses at the zero crossing from noise. But certainly worth a try. Is it better with the high amplitude signal?

As the amplitude rises, the phase of shifts and the jitter is reduced but not gone.

 

[crutschow]

.............................. Now the question is about an efficient schematic using a 4046 with sine wave or can I still use the TTL from the AGC and get it tuned even better to reduce the jitter? I am currently using the TTL with a 4046 on the schematic that I had above and it still has jitter in it. I am wondering if I can ever get the PLL output to be stable/close to the input sine wave (which is what I am looking for).

I don't see your schematic.

Jitter in the PLL VCO can be reduced by using a larger capacitor in the feedback loop. The downside is that makes it harder for the loop to capture the signal and lock to it.

 

[pavjayt]

I don't see your schematic.

Jitter in the PLL VCO can be reduced by using a larger capacitor in the feedback loop. The downside is that makes it harder for the loop to capture the signal and lock to it.

I uploaded my design rather than my schematic, its in Post#15. Actually I have 2 versions of my PLL design. Will upload other one soon.

thanks

 

[pavjayt]

Here is my alternate PLL schematic which has tuning control of center frequency and this works with a sine wave input where as my other design is a fixed one and works only with TTL input.

 

[alec_t]

I'm puzzled as to why you have all those caps in parallel/series? Isn't that likely to make the circuit less stable?