I would like to ask a question. I have generally seen from practice that the PMOS have larger (absolute) values of threshold voltage than the NMOS devices. Can this be explained by physics? Taking also into account the fabrication process (meaning that there are some differences between constructing a PMOS and an NMOS transistor.
The majority hole carriers in P material have a lower mobility (move more slowly for a given electric field) then the majority electron carriers in N material so that likely is a factor, but beyond that I don't know.