Clamper Circuit Design

[v1.5]

hi.
I am looking for a clamper circuit for my system design. I want to use this circuit in my future projects. This circuit already has a positive bias and I want to make this input signal positive clamp.
I made several researches on the Internet, but I could not find exactly what I was looking for. As you know, there are circuits containing various diodes and capacitors. When I applied these circuits, I found that the signal had the lowest voltage of -0.7V negative. However, I do not want my signal to drop to negative voltage.
Below I have drawn an example of the signal I have;

Below I have drawn how the output of the above signal should be;

First of all, I do not have a negative voltage source in my system, so I cannot make negative biasing. For this, I applied to various opamp circuits, but I couldn't find exactly what I was looking for.
Maybe there is a method or notes that you can show me....

 

[rjenkinsgb]

Just feed the signal through a moderate value resistor eg. 1K to 10K (in series) and connect a small FET such as a 2N7000 from the resistor output (next stage input) to ground.
With the FET off, the signal should be unaffected. With it on, it will be held at 0V.

Or you can use an analog switch IC to literally "turn off" the signal.

 

[v1.5]

Just feed the signal through a moderate value resistor eg. 1K to 10K (in series) and connect a small FET such as a 2N7000 from the resistor output (next stage input) to ground.
With the FET off, the signal should be unaffected. With it on, it will be held at 0V.

Or you can use an analog switch IC to literally "turn off" the signal.

A scheme would be perfect.
Thanks.

 

[v1.5]

Still looking for scheme or idea please ?

 

[Ylli]

How about something like this?

 

[v1.5]

How about something like this?
View attachment 126082

Good evening and thank you very much for your reply.
I was using this circuit before. But its stabilization was not always easy. For this reason, I started to search for more sensitive circuits. Unfortunately, I have not found a different circuit structure until now. After that, I think I will continue to use this circuit. Thank you, this is a more stable circuit than I used before. This evening I will try the circuit experimentally and write the result I got here.

 

[v1.5]

hi.
I apologize for the delay in the past few days. I tested the circuit in application and it has 200mV dc offset. Whatever I did, I could not get rid of this tension. Finally, I decided to use your circuit structure because I was able to achieve the least dc offset voltage that way. As I said, I still could not get exactly what I wanted, but as a last cure I decided to add this to the system.
Thank you for your answer and guidance.

 

[Ylli]

was able to achieve the least dc offset voltage that way

If you are refering to the circuit I posted, it a matter of balancing the DC load with the current through the 'reference' diode (lower diode). If your DC load is higher, you may have to reduce the current through the lower diode. and vice-versa.

 

[v1.5]

thank you .
I will try it this evening.