• Welcome to our site! Electro Tech is an online community (with over 170,000 members) who enjoy talking about and building electronic circuits, projects and gadgets. To participate you need to register. Registration is free. Click here to register now.

Can somebody please give me some ideas.

Status
Not open for further replies.

Dennisc

New Member
I've attached a scan of a problem I'm working on. I need to change this circuit to all NAND gates. I have no clue if what I've done so far is correct. It seems like to go to NAND you have to get rid of the +'s. Is this even close to correct the way that I've done it? Once I have converted this to a NAND circuit then I need to draw it. I would greatly appreciate any advice.
Thanks
 

Attachments

RadioRon

Well-Known Member
This looks like a lesson in reduction using identities and such. I notice an important reduction available in each example. The left hand figure includes the function A'+A'B. If you think about this for a bit, you may realize that this is equal to A'. Consider that if A=1, then A'=0 and the term A'B must also equal 0 (no matter what B is, a 0 ANDed with it will always be 0). If A=0, then A'=1 and the first term insures that the overall result will be 1. So basically, it doesn't matter what B is at all. So the overall equation can be reduced from A'+A'B+AC = A'+AC.

In the right hand example, I notice that we have a term DBD'. When you AND something with the inverse of itself, the result must always be 0. When you include a 0 term in an OR, it does nothing, so you can simply omit it. So the second equation reduces to (A'B+A'CD)'.

Both of these results are easily realized using NAND gates, since a NAND is simply an OR using negative logic at the input.
 

Dennisc

New Member
Thanks for the help. I have about 20 more problems like this to do before Wednesday night. I am trying to figure these two out and it looks like the first problem ends up A'+AC and problem two A'B+A'CD. It looks like problem two should end up with a line above it from the inverter on the end of it. If these are the two final answers then do I go from here and try to draw out the problem? Is this the place where I should DeMorgan the problems? Is this where I need ot get rid of the +'s to switch to a NAND gate? Sorry to ask so many questions, I am just having a hard time understanding this logic stuff. Once I get these first problems solved I am sure I will understand how to do the rest.
Thanks Dennis
 
Last edited:

RadioRon

Well-Known Member
Dennisc said:
Thanks for the help. I have about 20 more problems like this to do before Wednesday night. I am trying to figure these two out and it looks like the first problem ends up A'+AC and problem two A'B+A'CD. It looks like problem two should end up with a line above it from the inverter on the end of it. If these are the two final answers then do I go from here and try to draw out the problem? Is this the place where I should DeMorgan the problems? Is this where I need ot get rid of the +'s to switch to a NAND gate? Sorry to ask so many questions, I am just having a hard time understanding this logic stuff. Once I get these first problems solved I am sure I will understand how to do the rest.
Thanks Dennis
Yes, once you do that reduction, it is time to Demorgan to all AND or NAND. I would normally just start drawing gates at this point.
 

Dennisc

New Member
I attached again the same two circuits, I tried to DeMorgan them so I could write them with NOR gates only. Do these two circuits look like they're ready to draw or are there errors in them.

Thanks Dennis
 

Attachments

Status
Not open for further replies.

Latest threads

EE World Online Articles

Loading
Top