As far as I'm aware?, a wafer is just that - a large wafer of silicon that the chips are etched on to. The wafer is then cut into the individual dies for the chips.
As an intellectual exercise you might want to compute how many rectangles measuring L by W you can fit on a circular disc of diameter D. For extra credit you can compute the amount of waste as a percentage of the original area.
As an intellectual exercise you might want to compute how many rectangles measuring L by W you can fit on a circular disc of diameter D. For extra credit you can compute the amount of waste as a percentage of the original area.
Yeah, it's kinda like guys who can calculate the product of two huge numbers in their heads - neat trick, but who needs it?
Do I detect some cynicism from Papabravo?
LOL, and since generally everybody wants to see if they got the correct answer, we all check with a calculator, and hey presto, we could have got there in one step.
He reminds me of the kind of person who could always cut the tension at a meeting / boring seminar with a witty one liner. I always tried to sit beside those guys, made the event much more memorable, and I usually retained whatever it was I was supposed to get from the assemblage.
Well, I don't code, but that looks like the die area divided by the wafer area. Isn't that inverted? And it doesn't seem to account for the wasted partial dice around the edge, which is the hard part.
Like mentioned, it's a thin flat disc of silicon with circuits (ICs) that have been etched into the surface. It is how ICs are manufactured, and wafers are typically 8" or 12" discs (200mm and 300mm). Here's a picture of a wafer **broken link removed**
On edit, I actually have a wafer of old Itanium 64-bit processors. There are probably at least 50 processors on the wafer, and back in the day (when I got the wafer), those processors were going for over $1000 each!
i read somewhere that the early pentium wafers only produced about 30% of useable chips,which is (was?)why they where sooo expensive when they came out the factory...
I notice on the actual wafer that some chips just go right up to the edge and there are some empty spots. That's why I think this problem is more involved than it looks.
I notice on the actual wafer that some chips just goe right up to the edge and there are some empty spots. That's why I think this problem is more involved than it looks.
Well, I don't code, but that looks like the die area divided by the wafer area. Isn't that inverted? And it doesn't seem to account for the wasted partial dice around the edge, which is the hard part.
indeed - to be honest, i couldn't find this thread.
You are right, this is a tricky question, but quite simple to solve.
The wafer has to be subdivided in rows and columns, each with a l-distance and w-distance. Now you only have to check which subareas are of full size ( that means if(subarea == l*w) ..., or in words, which subareas are rectangular ).
Ok the hard part is to calculate these subareas. You could subdivide the circle into segments, each of an area given by:
**broken link removed**
One segment area can be calculated using this formula:
**broken link removed**
where \alpha is the angle defining the chord ( which is the lower ( and upper ) boundary of each segment ). So the exact area of one "cutted segment" is:
**broken link removed**
This is still not a rectangular area. It's left and right edges are curved.
So we need to calculate it... Such a segment has an upper and lower boundary. If we draw a stroke from the lower boundary of a segment A_{i-1} to the lower boundary of A_{i}, we can calculate the biggest rectangular area inside this segment. The lower boundary is called a chord ( can be seen as the width of the rect ), and the stroke we drew is simple its height. (chord)x(height) = rect_area. The area A_0 can never be used because its curvature is too big. Hence we start from A_{i}, with i > 0, which length is given by the lower boundary of A_0 ( or in general by A_{i-1} ) Putting this all together we get the following equation for the complete rectangular area of one segment:
**broken link removed**
where h_i is the height of one segment and s_{i-1} the length of the previous segment. h_i and s_i are defined by:
**broken link removed**
**broken link removed**
Hmmmm ... let me think. Ok these are the abstract equations to calculate the usable area on a wafer. To rewrite this in C++ code, you need to use for-loops and an array of \alpha_i ... that means unsigned int alpha; where i is the number of subdivisions. By h_i you have a function of alpha giving you the height of one segment... you can modify it to a function of h_i, giving you the numbers of subdivisons needed. If i've time, i will try to put this into code - Most likely there are one or two tiny errors in my equations. Please tell me if you find them
Ciao,
Alexander
~ Addition: If you want to calculate how much area of the wafer is wasted at a given IC size, you only have to subtract A_{(R)i} from the complete wafer area, which is simply given by the circle area: A_{circle} = r^2 \cdot \pi.
In terms of maths ( because i love it ):
**broken link removed**
boy i hope there are no errors....
and the expanded sum (1) could be simplified - but i'm neither able to do that right now nor i have the time...
and don't even think about correcting my spelling mistakes =)
yeah, i'm not in the process but i'm sure there need to be separation between 2 dies (to cut them) also you have tolerances of the etching machine of wich the planification would like to know with other words how many fails we could have??? etc. etc.
sure - but this will not decrease the number of dies fitting on the wafer.
but well ... you're right concerning the realisation of such a process.
If you formulate these equations with tensors, you'll get the (X|Y) values.
And there are some things which cannot be calculated exactly - like the number of fails... this depends on the accuracy of the machines.
no, thats the reason they are called fails, but you now the maximum accuracy, the minimum and the average sow some numbers can be made
also the separation does takeaway wafer space altough it would be a small thing, but for your program its not wasted space but needed space..sow your precentage wasted will be lower..