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Burst feature of a synchronous SRAM

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Karkas

Member
Hi, I've been studying a little about memories and I didn't understand the function of the burst feature, I guess I understood its functioning but not its importance and why is it necessary.

In the book says "when an external address is latched in the address register, the two lowest order address bits, A0 and A1, are applied to the burst logic. This produces a sequence of four internal addresses by adding, 00, 01, 10 and 11 to the two lowest order address bits on successive clock pulses. The sequence always begin with the base address which is the external address held in the address register.

The address burst logic in a typical synchronous SRAM consists of a binary counter and exclusive-OR gates. For 2-bit burst logic, the internal burst address sequence is formed by the base address bits A2 to A14 plus the two burst address bits A0' and A1'".

I can see that the four possible states (assuming that A0 and A1 are both 0, LOW) will be sequentially added to the external base address, but what is the point of that? I didn't see where did it say it. It says "this allows the memory to read or write at up to four locations using a single address", but what is the advantage of that?

How do they do if they only need to write or read in only a memory location?

Attached the two images.
 

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  • Synchronous SRAM.GIF
    Synchronous SRAM.GIF
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  • Burst Logic.JPG
    Burst Logic.JPG
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mneary

New Member
Synchronous SRAM was in use for a while but I haven't seen one in maybe 20 years. It was messy to work with but the trouble was (barely) justified if that was the only way to achieve the speed or storage capacity.
 

Karkas

Member
Well I was studying memory and storage and they had that point there, so the burst feature was for that?(speed or storage capacity).

do you think it is not very important for me to really understand it?
By the way, what's the type of RAM used in this times?
 
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