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Board Layout

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jimmythefool

New Member
Hi all, Hope you have nice weather too :)

I need to improve the layout of a PCB for transient immunity. Most of my inputs to my 16F887 comprise of a transzorb to 0v, 330R in series with the input, a 0.1 uf to 0v, and a 4K7 pullup. My intention was to put the transzorb as close to the connector as poss, the 0.1uF as close to the PIC as poss, the pullup next to it, and the 330Rseries resistor between them.
Is this the best way?? (Approx 4cm between connector and PIC

Thank you for any advice

Jim
 

dougy83

Well-Known Member
You'll need to include some more info, for both normal operating conditions and for expected fault/transient conditions such as signal rise/fall time/frequency/source impedance, signal type (analog/digital) etc.
 

jimmythefool

New Member
Ty for the replies..
Basically, I have 8 inputs on my pic, going to the external world. (Volt Free Contacts)For EMC, they will test the screened cables going to them. 1KV surge, 8KV ESD, and EFT, capacitive clamp I believe.


Regards
Jim
 

jimmythefool

New Member
ty for the reply :)

I don't really want to post my schematic on here. I was looking more for a 'rule of thumb. ie 'always placing the decoupling cap close to the IC, rather than close to the connector' etc


Thanks

Jim
 

dougy83

Well-Known Member
My rules of thumb:

* cap close to the connector to shunt any spikes to ground
* transorb close to conenctor
* resistor & inductor/ferrite-bead to pic input to reduce residual spike
* traces enter pad of cap/transorb from one side and exit from the other to minimise inductance to the protection device
 
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