We can do this with a hardware UART and an on chip timer easily.
J1708 uses RA-485 protocol @ 9600bps. One bit time = 104.2uS, which x11 is 1.14mS for 11 bit times (J1708 buss access time). A J1708 "message" consists of one message byte, up to 19 data bytes (known as "characters"), and one checksum byte for a total maximum of 21 characters per "message" (1 "character" = 1 "byte"). There cannot be more than two bit times between each character in the message (enough time for 1 stop bit and 1 start bit between bytes), and there must be at least 10 bit times between each message.
This means that when transmitting a message, you want to transmit all of the bytes within the message one right after the other (super easy to do), then after the last byte of the message is sent (the checksum byte), you must wait a minimum of 10 bit times before the next message is sent.
About that...each message also has a "priority" level, which is going to set the buss access time. The priority levels are 1-8 (with level 1 being the highest priority), and the buss access time for each message is 10 bit times + 2x the priority level of the message. So if the priority of the message is 1, we need 10 bit times + (2 x 1) = 12 bit times total. If the priority level of the message is 5, we need 10 bit times + (2 x 5) = 20 bit times total between messages.
Once the checksum byte has been received, we can use TMR0 to create a 1.14mS delay or we can construct a software delay for such to wait 11 bit times prior to transmitting the received bytes down the buss.
A couple of things we need to know -
1) What PIC are you using?
2) What oscillator config are you using and at what speed (i.e. internal oscillator, external crystal, etc etc)?
Setting the UART up is simple to do once you know your Fosc speed. But we need to know what Fosc speed is being used in order to know what value to write to the baud rate generator in the PIC (SPBRG).
Now...the difficult part...we're going to need a way to monitor the transmit buss for 10 bit times to ensure that the tx buss has been pulled high for that period of time. This is actually simple to implement if we tie a PIC I/O line to the tx buss and set that line as an input. We can use TMR0 to set up a 1.042mS delay. While TMR0 is running, the input line is monitoring the tx line and incrementing a counter that we initialize to 0 before running the sample loop. Each time the tx line goes low within that delay time, the counter gets incremented. Then once TMR0 overflows, we jump into an interrupt handler where we check the counter. If the counter value is anything other than 0, we know that something else accessed the tx buss in that time so we must reset the counter, reset TMR0, then wait again. However, if the counter still equals 0, then we know we can go ahead and transmit down the buss.
A little bit involved but definitely possible. Answer my above questions and we can proceed further with this.