biasing an NMOS

[Heidi]

Dear friends,

The above schemetic is to simulate an NMOS amplifier. It will have a drain-to-source current Id=0.5mA, gate-to-source voltage Vgs=2V, drain-to-source voltage Vds=9.5V.

I would like to connect a Sin signal voltage source with amplitude of 0.1mV to the NMOS gate terminal through a coupling capacitor, causing the gate-to-source voltage to be 2+0.1*sin(wt), with frequency of 60Hz. Could you please show me how to connect the signal source? Thank you!

I was connecting the sin voltage source as follows, but the voltage Vgs won't have an amplitude of 0.1V.

 

[Miles Prower]

"I was connecting the sin voltage source as follows, but the voltage Vgs won't have an amplitude of 0.1V"

I don't suppose it would. You have 10K in the tail there, and that introduces negative feedback that greatly reduces the voltage gain, and makes Vgs smaller than it otherwise would be. You need to bypass that 10K to get the full open loop gain. For a signal frequency of 60Hz, 2.2uF or more would do it.

 

[Heidi]

I have increased the capacitance to 3uF, but the result doesn't have much difference.

What I was trying to do is to use the first circuit as a basic dc biasing scheme, which has a dc biasing voltage of 2V between the gate and the source. Next I want to superimpose a sin voltage of 0.1V on the dc voltage, so the voltage between the gate and the source will be Vgs=2+(0.1)sin(wt).

According to my textbook, it says that a signal source may be connected to the gate through a coupling capacitor, but I don't know how to do it.

 

[Miles Prower]

I have increased the capacitance to 3uF, but the result doesn't have much difference.

What I was trying to do is to use the first circuit as a basic dc biasing scheme, which has a dc biasing voltage of 2V between the gate and the source. Next I want to superimpose a sin voltage of 0.1V on the dc voltage, so the voltage between the gate and the source will be Vgs=2+(0.1)sin(wt).

According to my textbook, it says that a signal source may be connected to the gate through a coupling capacitor, but I don't know how to do it.

"According to my textbook, it says that a signal source may be connected to the gate through a coupling capacitor, but I don't know how to do it".

You have already done this part.

"I have increased the capacitance to 3uF, but the result doesn't have much difference".

Next, you need to connect that 3.0uF capacitor between the source and the ground, or you can connect it in parallel with the 10K resistor. If you do that, you will see: Vgs=2+(0.1)sin(wt). So long as you have that negative feedback in there, you won't see the full Vgs.

 

[Heidi]

Hello, Miles, thank you for your simple and clear directions. It works!

I have a few more questions.

#1 In analysis, because the resistor Rg=1 Mega is pretty large, can we do the analysis with Fig.2, without Rg?

#2 Referring to Fig.2, the dc voltage Vss2 is in series with the ac voltage V8, whitch was described as 'conceptual' in my textbook. Can we connect the two voltage sources that way in practice?

#3 My original question arised from a statement in my textbook, it says:

Resistor Rg, Fig.3 below, establishes a dc ground at the gate and presents a high resistance to a signal source that may be connected to the gate through a coupling capacitor.

Is there another way to connect an ac signal source through a coupling capacitor and utilize Rg as a high input resistor?

 

[Miles Prower]

View attachment 84483

Hello, Miles, thank you for your simple and clear directions. It works!

I have a few more questions.

#1 In analysis, because the resistor Rg=1 Mega is pretty large, can we do the analysis with Fig.2, without Rg?

Yes, you can. A 1.0MEG gate return resistor virtually disappears for most signal sources that have a Zo << 1.0MEG, and that's why you want a 1.0MEG gate return resistor.

#2 Referring to Fig.2, the dc voltage Vss2 is in series with the ac voltage V8, whitch was described as 'conceptual' in my textbook. Can we connect the two voltage sources that way in practice?

You can do this only if your signal source has a path to DC, and that pretty much means a signal transformer. Any signal source that has an internal coupling capacitor will leave the gate floating. It's always best to include that gate return resistor. That way, you will never have a floating gate.

#3 My original question arised from a statement in my textbook, it says:

Resistor Rg, Fig.3 below, establishes a dc ground at the gate and presents a high resistance to a signal source that may be connected to the gate through a coupling capacitor.
View attachment 84484

Is there another way to connect an ac signal source through a coupling capacitor and utilize Rg as a high input resistor?[/quote]

That's what you have here:

The Rg is your high input resistance, and you have the coupling capacitor. You may or may not need that coupling capacitor, but it's always a good idea to include it unless you are certain that you will never connect to a signal source that has a DC offset. Any DC offset upsets your Q-point bias, and could render the voltage amp inoperative.

 

[Heidi]

That's what you have here:

View attachment 84507

The Rg is your high input resistance, and you have the coupling capacitor. You may or may not need that coupling capacitor, but it's always a good idea to include it unless you are certain that you will never connect to a signal source that has a DC offset. Any DC offset upsets your Q-point bias, and could render the voltage amp inoperative.

But if the capacitor were connected between the signal source and the gate, the amplitude of the voltage Vgs would much less than 0.1V, that won't suit my goal which I want the voltage between the gate and the source to be Vgs=2+0.1*sin(wt).

 

[Heidi]

Suddenly I realize that maybe this arrangement is what you meant:

With two capacitors, the voltage Vgs between the gate and the source terminal is approximately equal to 2+0.1*sin(wt):

I don't suppose it would. You have 10K in the tail there, and that introduces negative feedback that greatly reduces the voltage gain, and makes Vgs smaller than it otherwise would be. You need to bypass that 10K to get the full open loop gain. For a signal frequency of 60Hz, 2.2uF or more would do it.

Maybe you HAVE provided me with the solution but I didn't get your point!

Thank you!

 

[Miles Prower]

^^

Yep, that's it.