The FET models in LTSpice are behavioral they don't model silicon you can't simulate avalanche directly. Using a zener set to the avalanche voltage should work fine, then all you have to do is measure the power dissipated in the zener and determine if that's safe for your FET. It's not going to be exact but it will put you in the ballpark at least, make sure you model as many parts of the resistance in the real circuit as possible as that's going to drastically effect the peak power through the zener and that's what you're really looking for.
The main problem it won't show you is the reverse recovery characteristics of the FET's parasitic diode, which could cause latchup conditions or lots of ohmic heating if the FET gets stuck in it's saturation region during high frequency switching.