Good choices so far. FR4 will be fine, although even 50thou can be pretty wide when interfacing to small packages. Most parts are designed with hopes of getting into cellphones and the like where 8 to 12 layer boards are the norm, with 4 thou layers and very narrow 50 ohm lines.- yes, I am making a PCB for this, etching myself with the P&P method. Of course, I cannot get the same tolerances as a board house, but I can now get consistant results for 10/10 mil spacing. I'm using 0603 SMT passives, mainly because of the high frequency but also, for the inductors, thats the biggest size I can get them inI've designed with 0603 before, no problem there
As for the specs of the laminate, it is double sided FR4, 0.032" thickness, 1oz copper. From what I have gatherd from my research into microwave circuits, this is the 'bare mininum' requirment. Not only must there be a ground plane on the bottom side, but also the thickness reduces the width of 50 ohm transmission lines (down to 50mil). However, I am not planning on routing any RF carrying traces more than a few mm, with the possible exception of the antenna trace, to an SMA.
OK, good enough reasons.Reason for using this particular IC? Well, good point! .....
The BFG425W data sheet I looked at showed an output Z of around 70-j35 ohms or so. Did you do that analysis right? I agree that the chip input Z is a bit odd. Its also odd that they say the typical input is 2.6+j0 in the table, then 2.6-j2.6 in the pin descriptions. -j2.6 ohms is the impedance of a 25pF capacitance to ground and I suppose that this is not an outlandish amount for an IC pad.I asked RFMD for a second reference design (the one you saw) purely because I'm happier having more examples to see what is done, and any common little sub circuits between the two. Also because, with my limited knowledge of RF/microwave (and dare I say, even analogue) the input impedance of the RF input seemed terribly low, at 2.6-j2.6. When I used a smith chart to analyse the matching network, it seems the output of the BF425W based LNA was even lower, at around 1.6+j20.
A good idea, much more modular. An L match from 50 down to 2.6 is in order I guess.If I can sort out a matching network for 50 input, I can 'tinker' with external LNA's, the datasheets for which all seem to have nice reference schematics to provide a 50 output imedance. This is opposed to designing a matching network specifically for one LNA.
Sorry but "being overly cautious" and "no plated vias" don't go together in my book, but nonetheless, you might get it to work. Wired vias require more room than good plated through vias, so your ground paths from component to plane will be longer which adds series inductance which is not good (except when grounding an inductor of course).I would copy the reference design, but etching my own boards means no plated vias :/ a few of which are under the chip, but I am certainly using as much as I can of it, only changing the LNA and RF switch due to availability. Perhaps I am just being overly cautious here, after all I am only using RFsim99 to simulating matching circuits, and frankly, I don't trust it completely
Its all a matter of perspective. There is no difference between a series capacitor and a shunt capacitor if the capacitor is the only element in the load. I admit that this is not the case when the impedance is described as 2.6-j2.6, but, to simply make a point that most of the input Z is the terminal capacitance, I was sort of ignoring the 2.6 ohms of resistance since it is quite low.Btw the -j2.6 is a 25pf capacitance in series, at least by my understanding.
Go ahead and compile it. I have a feeling that with all these examples, we should be able to make a good estimate of the chip input Z.So, it looks like this is all on hold until I get a ball park figure. I am afraid I am unsure exactly how to work out an 'unknown' load impedance, from a known source impedance and matching network, I have only ever calculated things from the load side. If you know a way to work this out, I would be gratefulIf needs be I'll compile an image of the 3 'example' matching networks - although two of them are matched to two different LNA's, who's output impedance is also unknown. They are pretty basic but make quite pretty wide circles on a smith chart.
I have one that would be useful, but the logistics of getting your circuit to me and then back again are just a bit too much, I suspect, since I live in Vancouver.I wish I knew someone who owned a vector network analyzer, who I could buy a pint for.
Can I assume that you are using a gerber viewer to look at those?About the PCB traces, I have the gerbers for the second two matches, alas the 'photo's of the boards provided in the two ref designs are not the same, seems they took the snaps of earlier revisions, but the gerbers seem up to date.
its perfectly reasonable to guess that you will need an L or Pi topology for the matching and so just place three parts in pi configuration and then later do some educated guesswork and trial-and-error. Soldering parts on and off to optimize a tune is standard procedure in this business (but usually we start very close).Anyway, thankyou so much for taking the time/effort to look into thisI shall start work on the PCB adding some extra placements for passives in the network, whilst waiting for RFMD to reply. A few weeks down the line, if I am still none-the-wiser, I'll bite the bullet, etch a few boards, and start soldering on certain values to see how it functions (if at all...).
I have one that would be useful, but the logistics of getting your circuit to me and then back again are just a bit too much, I suspect, since I live in Vancouver.
Can I assume that you are using a gerber viewer to look at those?
If I assume the input Z to be, say, 8-j39, it is easy to get there from 50 ohms with two components. I only hope that you do everything you can to keep traces short, pads small and so on.
You mentioned co-planar before and thats fine, but you really should stitch the top layer ground plane to the lower ground plane at numerous places, and since you are using wire vias, that is going to be fair bit of work.
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