Adding fixed amount of clock cycles delay to a signal?

[unclejed613]

use Q9 only or use the shifted bit only, but not both.

 

[crutschow]

I see a notch in the ramp which I cna understand, but is there anyway to make this flat rather than looking like in the attachment?

You can hold the counter at zero during the SR delay (hold the 4040 Reset input high).
That could be done with a flip-flop or latch which is set by the counter zero output to hold the counter at zero, and reset by the SR output to start the count.