AD9850 calculation

[SwingeyP]

Hello.

I am trying to figure out how the equation for the AD9850 works.

The data sheet -->http://www.analog.com/static/imported-files/data_sheets/AD9850.pdf describes the formula on page 8

This VERY USEFUL utility -->http://designtools.analog.com/dt/dds/ad9850.html tells you what the 5 words should be for a given frequency.

I have attached some code.

I would have expected the fout to correspond some way to the four data bits to be sent. If I put these values into the utility I get something in the 60mhz range :-(

I feel my maths is all wrong.

Also I'll need to split the fout into 4 words - I was thinking a function that would loop 8 times with shift right on each of the bits. Can you do this to a variable? Examples only seem to do this with a port.

Can someone point me in the right direction with the maths please? (maths failure at school)

Regards - Paul

 

[ericgibbs]

hi Paul,
Downloaded your data, but I dont have Oshonsoft FP maths for Fout, so will see what I get with a Long Integer.

Can you post a screen image of the Tool Utility with the values you are using.?
E

 

[JimB]

The AD9850 uses 40 bits to set it up.

32 of the bits set the frequency, and 8 bits set the phase and power down state.
The 8 control and phase bits can just be set to zero.

To set the frequency, the 32 tuning bits are set as:

(Frequency x 2^32)/DDS Clock Frequency

Where the DDS has a 125Mhz clock, this resolves to

Bits = Output Frequency x 34.35973837

So to set the output of the DDS to 7.000Mhz, the tuning bits must be set to 7000000 x 34.35973837 = 240518168 or E560418 in Hex.

Does this help?
These things can be a bit confusing until you are familar with them

JimB

 

[Ian Rogers]

Can't possibly work.... 7Mhz + 100khz + 6hz = 7100006 * 125mhz = (A lot more than a long )

 

[ronsimpson]

I don't know about your part but the ones I have used work like this.
Inside there is a "adder" that adds two numbers every 125mhz.
W1,W2,W3, and W4 is the inputs to the adder.
Every time the adder caries out the output completes one cycle.
so:
If the internal adder has a 0 and the W1-W4 has a 80,0,0,0. Every clock we add 80,0,0,0 hex.
0,0,0,0 +80,0,0,0=80,0,0,0 MSB=0
80,0,0,0,+80,0,0,0=0,0,0,0 MSB=1
0,0,0,0 +80,0,0,0=80,0,0,0 MSB=0
80,0,0,0,+80,0,0,0=0,0,0,0 MSB=1
0,0,0,0 +80,0,0,0=80,0,0,0 MSB=0
80,0,0,0,+80,0,0,0=0,0,0,0 MSB=1
The output frequency is 62.5mhz.
This can be tested by going to http://designtools.analog.com/dt/dds/ad9850.html and put in 80 in w1 and 0 in w2-w4.

If you enter a number 1/2 as big then:
0,0,0,0,+40,0,0,0,=40,0,0,0 MSB=0
40,0,0,0+40,0,0,0=80,0,0,0 MSB=0
80,0,0,0+40,0,0,0=c0,0,0,0 MSB=1
c0,0,0,0+40,0,0,0=0,0,0,0 MSB=1
0,0,0,0,+40,0,0,0,=40,0,0,0 MSB=0
40,0,0,0+40,0,0,0=80,0,0,0 MSB=0
80,0,0,0+40,0,0,0=c0,0,0,0 MSB=1
c0,0,0,0+40,0,0,0=0,0,0,0 MSB=1
The output is now 31.25mhz

If W1-4=0 then 0+0=0 and the frequency =0

To further test this enter 0,0,0,1 which is the smallest number.
The F=.029hz T=34.5 seconds

This can be worked out in frequency or time. I usually use time.
Tout=34.5seconds/N Where N is the number you enter.

Hope this helps. Ron

 

[SwingeyP]

Experience is directly proportional to the value of the equipment ruined - I like this

Thanks Jim B. I felt it was something to do with transposition of formula which I have always been terrible at. I guess once I have this figure could run it through a function to split the 4 8 bit words, something like a shift right within a loop.

I understand the first 'control' word made of 5 bits for the phase and 1 bit for the power up/down, and the last two leave well alone. - I just set it to %10000000 which gives 180 degrees. Then follow this with the 4 words for the data.

I'll give the new formula a go later and see what happens.

Cheers - Paul.

 

[SwingeyP]

The thick plotens.

I have the output to the AD9850 sorted with a fixed frequency of 7.1Mhz. However its VERY unstable as can be seen here.

Can anyone see if this is a code issue or is the birds nest itself creating stability issues. Maybe noise on the (rather long) data lines?

I have attached the code but you can ignore the first bit. It's really just the loop that's doing anything.

Also another point I couldn't get the w_clk to pulse at all. It was always low. I have used a 10k pull up on this pin to ensure I get a pulse. Maybe this pin wasn't a good choice for this. Does it make any difference?

Cheers - Paul

 

[SwingeyP]

Should have said the pin used for w_clk is RA4 on a 16F876.

 

[ericgibbs]

Should have said the pin used for w_clk is RA4 on a 16F876.

RA4 is switching in simulation. As you know its open drain, so the pull up should be OK

EDIT:
Check the d/s for the ADCON1 reg setting and CMCON

 

[ericgibbs]

hi Paul,
You need CMCON= 0x07 in order to make PORTA digital.
Insert it under the TRISA = 0x07
E

 

[JimB]

I think that the problem is with the program.

The Ad9850, once set should not need to be repeatedly written to.
In my DDS test oscillator, the PIC goes to sleep until I change the frequency.

The ratsnest wiring is not a problem from a frquency stability point of view, but may cause problems for the integrity of the data being written to the 9850.

I think your problems are either due to the program going off into the realsm of fantasy and writing nonsense to the 9850, or data is getting corrupted on its way down the wires.

JimB

 

[SwingeyP]

Ahhh it's a 16f876 no comparators. Is the 'All Digital' sufficient?

 

[SwingeyP]

Thanks Jim,

I'm going to build a veroboard version later today (im just graph papering it now). That should eliminate any noise problems. I'll change the test code to write once without the loop and see what happens.

Cheers - Paul

 

[JimB]

Picture of my DDS oscillator are in this thread:
https://www.electro-tech-online.com/threads/dds-signal-generator-module.138465/#post-1148288

JimB

 

[ericgibbs]

Ahhh it's a 16f876 no comparators. Is the 'All Digital' sufficient?

It will come up in default with the comparators enabled. use AllDigital or CMCON=0x07

 

[SwingeyP]

It would have helped if i'd have attached the code too ....

 

[SwingeyP]

Once again this project has driven me to the edge and back. I have fixed the stability issue. It seems no matter what you tell the 16F876 (not A version) to do with the ADC pins they still cause some sort of interference. I tried All Digital CMCON ADCON1 nothing made any difference. In the end I moved to PORTB and everything is fine and dandy (so far). This does however leave me with a problem in that i'm rapidly running out of pins on the microcontroller. I might have to move up to an 16F877A (40 pin) if I want things like split VFO, Memory channels, Band selection etc etc. Anyway another learning curve hurdle has been jumped.

Thanks for all the help. so far.

Cheers - Paul