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A Much Improved Phase Locked Loop

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alisarhangpour

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Yesterday, I posted a topic on a PLL (https://www.electro-tech-online.com/threads/phase-locked-loop-using-micro.33930/), which was to lock to the mains 50Hz frequency, and some of you friends put good replies there, after saying thank you all, I'm going to tell that, after working on the design for around 9 hours today, I finally was successful to design a good PLL. Here the full detail comes:

1. First of all, the mains sine wave is converted to a square wave using op-amps.

2. I switched to Atmega64, because it has two 16 bit timers and so I can have better frequency resolution. The first one is to make a 12Khz PWM waveform and also measures the input frequency, the second one is the heart of the PLL.

3.A sine wave lookup table is included, which has 100 elements, a pwm_pointer variable shows where in the lookup table we are at any time. Timer 3 acts as the sine wave generator, for a 50 Hz sine wave its register value must be TCNT3=65535-2400, because:12Mhz/50=240k, 240k/100(samples)=2400.

4.The rising edge of the square wave described above, triggers an interrupt, within the interrupt service routine we look at the pwm_pointer, a pwm_pointer between 0 to 50 means our internal sine wave is leading the mains sine wave, a pwm_pointer between 51 to 99 means lagging.

5.So, in the case of leading, internal sine wave has to slow down, and vice versa. The speed of speeding up/slowing down depends on how big the phase difference is, and a variable delta_phi is created to correct the frequency.

6.The variable 'prescale', changes the period of sine wave samples and so corrects the sine wave frequency.

7.I've used a 12Mhz crystal. And Timer 1 is set as phase correct pwm, top=ICR1. so, to have a 12Khz PWM, ICR1 is set to 500 (12M/(2*500)=12k). The samples in the lookup table are from: 250+250*sin(2*50*pi*t).

8.If our internal sine wave is out of phase for 10 cycles, a frequency measurement is done, to compensate probable frequency changes in the mains. The variable 'delay' is employed to keep the number of cycles of being out of phase. And the variable 'period' has the mains frequency inside it (for f=50 Hz, period=12000(12kHz is the rate of overflow in Timer1)/50=240 so we have to multiply it by 10 to have the number 2400 mentioned in line 3 above).

After filtering the output PWM generated by the Micro, I was nearly shocked to see a very very stable sine wave with very small phase difference with the mains sine wave, and nearly no oscillations at all!
After that, I used a signal generator to be able to change the input frequency, and the pll tracked the input sine wave very well. it works so well for a wide range of frequencies, say, any frequency under 100Hz, which is absolutely enough for my purpose. For higher frequencies, the frequency measurement error will increase as well. I have attached the entire source code in C, written using Codevision AVR. If any one has any idea to improve this design, I will be very glad to be informed.
Good Luck.
 

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