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A Clock Speed Question

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k_noe

New Member
Hello,

I have a question about clock signals. I know you can step down a clock signals using divide by counters or with flip flop circuits using basic gates. I was wondering if it is possible to go the other way and step up a clock signal. For example can I somehow generate a 40Mhz signal from a 10Mhz crystal clock oscillator. On a related note, how do computers operating in the gighertz speed generate their clock signals because I don't believe crystal oscillators can generate signals as high as this.

If anyone have any thoughts or links on this it would be appreciated.
Thanks.
 

pebe

Member
You can increase the frequency with a couple of ex-or gates.

If you feed the 10MHz signal direct to an ex-or gate's input, and the same signal (via an RC combination to delay it) to the other input, you get a pulse from its output whenever the input polarity changes. So at the leading edge of the pulse you get a pulse at the output. The same for the trailing edge, so you now have two pulses for your original single pulse, and you have doubled the frequency.

Now take those two pulses to a second gate wired similarly and you get four pulses, or 40MHz.
 

NaN

New Member
Alot of the times a phase locked loop (PLL) is internally employed by chips to do this. By properly selecting a divide by N in the feedback path of the PLL loop, the loop frequency generator will have to generate a N time higher frequency to compare to the external reference signal.

Ie. you put in 10Mhz, the feedback path is divided by 4, then the internall frequency generator is 4*10 Mhz = 40 Mhz. When divided down to 10Mhz, its phase is locked with the crystal reference, ensuring a stable 40 Mhz before the internal division.

Hope this helps..
NaN
 

Dean Huster

Well-Known Member
The "olden" days

In the 1960's, they didn't have all the PLL circuits (well, save for the old AN/URC-32 transceiver used by the U.S. Navy) and digital chips (ICs had yet to be invented) to do things like this. They used traditional "radio" methods of doing this. Beginning with a crystal-controlled oscillator, they would feed the signal to an amplifier operating in a non-linear mode which would generate several harmonics, such as X2 or X5. The output of this circuit was fed to a tank circuit tuned to the harmonic needed. For instance, they might start with a 1MHz standard frequency and double this to 2MHz. Then they'd feed that 2MHz to another such circuit to get a fifth harmonic, 10MHz. That one might go to another doubling circuit to get 20-MHz and finally that output to a quintupler to get 100MHz. If they needed clean sine waves, they'd always send those signals through one or two more tank circuits tuned to the desired frequency. The AN/USM-207 frequency counter multiplied 1MHz up to 100MHz for use in the gating circuit in this way. These circuits were known as frequency multipliers (frequency doublers, frequency triplers, etc.) and were very common in communications equipment. It was a wonder way to get clean sine wave signals with the same precision as the original reference frequency.

Dean
 

k_noe

New Member
Thanks for the replies. I'm not to familar with PLL circuits so I need to read up on it. I was thinking up various complicate ways to do this, the ex-or gate solution is so simple and straightfoward it would never have occurred to me.

Thanks.
 
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