Hi,
Parallel binary to parallel BCD has a one to one mapping, so i would think regular logic
gates like OR, AND, NOR, AND, NOT should do it one way or another.
Here are the beginning logic statements for outputs A through E. These can
be simplified greatly to reduce the number of gates. Note that these statements
are for only 4 bits input, not 5. You'll have to solve that yourself
This is just an example of one way to get there...
Code:
ab'c'd'e'+abc'd'e'+ab'cd'e'+abcd'e'+ab'c'de'+abc'de'+ab'cde'+abcde'
a'bc'd'e'+abc'd'e'+a'bcd'e'+abcd'e'+a'b'cde'+ab'cde'
a'b'cd'e'+ab'cd'e'+a'bcd'e'+abcd'e'+a'bcde'+abcde'
a'b'c'de'+ab'c'de'
a'bc'de'+abc'de'+a'b'cde'+ab'cde'+a'bcde'+abcde'
As an example of how much these might simplify, the first (top) statement simplifies to one
input: a
which of course is bit 1 of the input.
Each term of the above statements is made by observing what logic state is required to get a '1'
on the output for that bit when it is required. If the input bit is '1', then use the letter, if '0' then
use the letter negated.