2 ESP32's GPIOs to same header pins isolation

[StealthRT]

Hey all I am wondering if my idea below would work.

What I am wanting to do is connect 2 (really 3 ESP32's and 4 ATmega32u4's) micro controllers (in the example there are just 2 ESP32's for simplicity) and they both connect to the same header pins.



I know that this would not work if both ESP32's were powered on but would this work if only 1 of the ESP32 were to be powered while the other has no power?

I was unsure if this type of setup would cause an issue with one another? Or if this setup is fine as long as one is turned off?

If this would not work what could you suggest I can use in order to isolate the 2 ESP32's from each other? I was thinking a multiplexer but that would just allow 1 GPIO pin to then have 16 more GPIO pins for it.

I was also thinking about some type of reply but that would be a lot of relays to since the ESP32 has 25+ GPIO pins that I would connect to the headers.

There was another thought of using some type of optocoupler but like the suggestion above, this would also have many of them for the 25+ GPIOs.

Suggestions or confirmation would be great! Perhaps a IC that I have not heard of before that would be a good fit for this? Don't want to blow either up

Disclaimer: Also posted on
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allaboutcircuits.com

 

[rjenkinsgb]

Sorry, that cannot work.

The I/O port protection diodes within the "unpowered" device would conduct and try to power the device via the I/O pins, either pulling the signal voltage down or damaging the device.

Without knowing why you are wanting to interlink them, eg. what signal directions and speeds are, how long the interconnections will be etc., it's not really possible to suggest a method.

It could be as simple as diode OR'ing signals, if everything is unidirectional and the connections are relatively short, for the signal speed?

 

[danadak]

If all devices powered one could be active with the others in Tristate on
common signals. You would of course need a protocol when all parts
powered up to initialize their GPIO to tristate then assignment of which
one becomes active master.....Most processors these days power up
with GPIO tristated, or as inputs or a combination of both

This is tricky as you need to know how the exact power up sequence
works for the processors, may require a common clock to work. Eg, when
they started up, because of internal PLLs and their clocking, and if they have a
guaranteed all GPIO tristated on power up, if that sequence is basically
synchronous, so that no MCU has out of spec rail current, even temporarily,
causing internal; power rail spikes and possible state machine errors.

Or use external buss logic and control that after all have powered up.


Regards, Dana.

 

[StealthRT]

If all devices powered one could be active with the others in Tristate on
common signals. You would of course need a protocol when all parts
powered up to initialize their GPIO to tristate then assignment of which
one becomes active master.....Most processors these days power up
with GPIO tristated, or as inputs or a combination of both

This is tricky as you need to know how the exact power up sequence
works for the processors, may require a common clock to work. Eg, when
they started up, because of internal PLLs and their clocking, and if they have a
guaranteed all GPIO tristated on power up, if that sequence is basically
synchronous, so that no MCU has out of spec rail current, even temporarily,
causing internal; power rail spikes and possible state machine errors.

Or use external buss logic and control that after all have powered up.


Regards, Dana.

Do you have any suggested IC's for doing the buss logic?

 

[Nigel Goodwin]

Perhaps you're care to explain EXACTLY what you're trying to do, and why?, as it depends entirely on that.

 

[StealthRT]

Would something like the 74HC157 be a good choice? I’m reading the data sheet on it and it seems to allow 4 gpio + 4 gpio and outputs one of them. But I’m not seeing anywhere about if it can do digital and analog since the gpio would be one or the other. Aside from that I’m also not seeing anywhere where the company makes a larger version that would have do more than 8 inputs.

 

[danadak]

Do you have any suggested IC's for doing the buss logic?

If you cant guarantee processor will come up tristated you just need a set of
buffers to control, that cause the tristate condition at the common shared
connection points.

So just take a look here at tristate buffes, with an enable of course :

https://www.onsemi.com/products/timing-logic-memory/standard-logic

Regards, Dana.

 

[For The Popcorn]

Analog signals will be a problem.

 

[StealthRT]

Is there any ic that just let’s the line go straight thru without any degrading of the signal be it digital or analog? Of course I would need to and able to turn off the flow?

 

[danadak]

Yes, analog switches would work as well. But you have to pay attention
to thinks like Ron of the switch, speed depending on what you are
doing.

https://www.onsemi.com/products/interfaces/analog-switches#products=fnN0YXR1c352YWx1ZX4zfiF+TGFzdCBTaGlwbWVudHN+IX5MaWZldGltZX4hfk9ic29sZXRlfg==

Regards, Dana.

 

[StealthRT]

Thanks for all the replies! I'm going back to my drawing board to figure some things out with the knowledge I now have. Thanks!