initUartMasterMode:
banksel BAUDCTL ; bank 4
bcf BAUDCTL,SCKP ; data changes on rising edge of clock
banksel TRISC ; bank 1
movlw b'11000000' ; RC6-RC7 tristate (controlled by UART hardware)
iorwf TRISC,F ;
movlw d'34' ; 115.2kbps bit rate w/16MHz xtal (2% error)
movwf SPBRG ;
movlw b'10110000' ; synchronous serial, master mode
movwf TXSTA ;
banksel RCSTA ; bank 0
movlw b'10000000' ; enable serial port, continuous receive disabled
return ; done
initUartSlaveMode:
banksel BAUDCTL ; bank 4
bcf BAUDCTL,SCKP ; data changes on rising edge of clock
banksel TRISC ; bank 1
movlw b'11000000' ; RC6-RC7 tristate (controlled by UART hardware)
iorwf TRISC,F ;
movlw d'34' ; 115.2kbps bit rate w/16MHz xtal (2% error)
movwf SPBRG ;
movlw b'10110000' ; synchronous serial, slave mode
movwf TXSTA ;
banksel RCSTA ; bank 0
movlw b'10000000' ; enable serial port, continuous receive disabled
return ; done