To get 50 Hz with the same accuracy as the power line, you could use a PLL. Rectify the 9V 60 Hz, and also feed the 60 Hz to a divide by 6 circuit. Feed this 10 Hz into one input of a 4046 PLL phase detector. Set up the timing capacitor on the 4046 so its center frequency is 100 Hz. Take the PLL's 100 Hz, divide it by 10 and feed it to the other input of the phase detector. Use phase comparator II. Make your loop filter greater than 1 second. Take the 100 Hz VCO output, divide it by 2 (to assure symmetry) and drive a low-power h-bridge, and pass it on to the clock. It probably won't mind a square wave.
If you do this all in old fashioned CMOS, it may not need level translators. (But use good static handling procedures).