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÷Number. 4000 series

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axro

New Member
I'm playing around with a 4060 14bit Ripple counter. But alot of the 4000 series have a ÷SomeNumber outputs.

I know that if it is ÷16 for example that, that port puts out pulses(an equal low and high) at 1/16 of clock frequency. My question is this:

On a Ripple counter at least, does the pulse start at low or high? The reason I ask is because I notice it turns high at half of what you(or at least I) would expect the count to be. For example.

Q4 turns on at a count of 8 and off at 16 and then on again at 24 at off at 32.

Q5 on at 16 off at 32 on at 42 off at 64.

Is that start of all pulses actually at 0 master clock pulses? And then starting a new cycle(starting low) at their ÷ by number?
 

ericgibbs

Well-Known Member
Most Helpful Member
I'm playing around with a 4060 14bit Ripple counter. But alot of the 4000 series have a ÷SomeNumber outputs.

I know that if it is ÷16 for example that, that port puts out pulses(an equal low and high) at 1/16 of clock frequency. My question is this:

On a Ripple counter at least, does the pulse start at low or high? The reason I ask is because I notice it turns high at half of what you(or at least I) would expect the count to be. For example.

Q4 turns on at a count of 8 and off at 16 and then on again at 24 at off at 32.

Q5 on at 16 off at 32 on at 42 off at 64.

Is that start of all pulses actually at 0 master clock pulses? And then starting a new cycle(starting low) at their ÷ by number?
hi,
Some counters like the 4024 and 4060, clock on at the High to Low transition of the clock.:)

All output start low... BUT to ensure this, the counter should be Reset at power up.
 
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MikeMl

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I'm playing around with a 4060 14bit Ripple counter. ...
Is that start of all pulses actually at 0 master clock pulses? And then starting a new cycle(starting low) at their ÷ by number?
There is no guarantee that any IC flip-flop counter will start with all bits at zero, unless there is an explicit RESET pin, or built-in reset circuitry which is specifically called out on the data sheet.

If you are simulating a counter, a real Logic simulator has the capability of representing a logic low, high, and UNDEFINED, meaning that it doesn't know if a given node is high or low (yet). If you model a counter in a Logic simulator, and never force a reset, it will count forever with all bits being undefined...

If you use Spice to simulate a logic flip flop or counter, it unrealistically starts with all bits at zero. This doesn't happen in real life!!!
 

axro

New Member
I guess I'm even more confused now. I've realised that if I plug in my ciruit random lights turn on right away. But if I disconnect the reset pin and then plug in back in everything goes blank and starts counting from the beginning.

So are the start of the pulse that the ÷ by outputs make low or high? i realize that each pulse cycle lasts 16(in the case of Q4) master clocks cycles. 8 being high and 8 being low. Lets put it this way.

I reset the chip, it starts counting at 0. Q4 is low. At clock pulse 8 it goes high and at clock pulse 16 it goes low again. Is clock pulse 0 the start of Q4's ÷ 16 pulse or is pulse 8(high) the start?
 

ericgibbs

Well-Known Member
Most Helpful Member
I guess I'm even more confused now. I've realised that if I plug in my ciruit random lights turn on right away. But if I disconnect the reset pin and then plug in back in everything goes blank and starts counting from the beginning.

So are the start of the pulse that the ÷ by outputs make low or high? i realize that each pulse cycle lasts 16(in the case of Q4) master clocks cycles. 8 being high and 8 being low. Lets put it this way.

I reset the chip, it starts counting at 0. Q4 is low. At clock pulse 8 it goes high and at clock pulse 16 it goes low again. Is clock pulse 0 the start of Q4's ÷ 16 pulse or is pulse 8(high) the start?
hi,
Confirm which type you are using in your test.?

A method to get a power on Reset, is to connect the MR line to the +Vcc rail via a 10nF cap and a 10K from the MR to 0V.
This drives the MR pin high at power up which Resets the counter to zero.
 

MikeMl

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If you do not explicitly reset a counter at power up, its bits will come up in a random pattern. How many clock cycles it take for the nth bit to change is a function of what bit pattern all the lower bits came up in.

If you are using the counter to generate a delay, and you care that the timing period be correct the first time the counter cycles, you have to RESET it at power up!
 

axro

New Member
Confirm which type you are using in your test.?
I am using a CD4060 with clock provided by an Astable 555. The 555 is also driving a CD4026 with a 7 segment display attached so I am able to count the pulses. I know that the 4060 advances on low and 4026 on high, but I at least get a good idea of what pulse I'm on.

I reset by diconnecting the reset and reconnecting it again.

If you do not explicitly reset a counter at power up, its bits will come up in a random pattern. How many clock cycles it take for the nth bit to change is a function of what bit pattern all the lower bits came up in.

If you are using the counter to generate a delay, and you care that the timing period be correct the first time the counter cycles, you have to RESET it at power up!
I am resetting it. Manually for right now, just for my tests.
 
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MikeMl

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I reset by diconnecting the reset and reconnecting it again.
NEVER, NEVER, NEVER attempt to assert any CMOS logic input by "disconnecting" it!!! A floating CMOS input acts is a high-impedance antenna for electrostatic fields, and can float high, low or anywhere in between, likely at 60Hz due to pick-up of the power line. There is no predicting if it will act correctly.

The correct way of feeding a pulse to a CMOS input depends on if the pin is "active high" or "active low", and if the input is "level-sensitive" or "edge sensitive".

If the pin is "active high, level-sensitive" then tie the input low using a 1K to 100K resistor between the pin and VSS (ground). Now if you want to momentarily pulse the pin High, leave the resistor in place and use a clip lead to momentarily short VDD to the pin.

If the pin is "active low, level-sensitive" then tie the input high using a 1K to 100K resistor between the pin and VDD (positive supply). Now if you want to momentarily pulse the pin Low, leave the resistor in place and use a clip lead to momentarily short VSS to the pin.

If the input is "edge-sensitive" you have to use a one-shot multi-vibrator or toggle circuit to generate a clean pulse. Attempting to use a clip lead will usually produce multiple short pulses which will create predictable results. Try pulsing the clock input to your counter with a clip lead and you will see what I mean.
 

kpatz

New Member
I know that if it is ÷16 for example that, that port puts out pulses(an equal low and high) at 1/16 of clock frequency. My question is this:

On a Ripple counter at least, does the pulse start at low or high? The reason I ask is because I notice it turns high at half of what you(or at least I) would expect the count to be. For example.

Q4 turns on at a count of 8 and off at 16 and then on again at 24 at off at 32.

Q5 on at 16 off at 32 on at 42 off at 64.
If you only look at the high-to-low transitions, ignoring the low-to-high transitions, you'll get the correct divisions. (Q4 = high-to-low after 16 clocks). Since the chip responds to the high-to-low transition on the clock pin, it is working the way you'd expect.

In case you're wondering how a ripple counter works:

Think of a how a toggle flip-flop works. When the input goes from high to low, the output of the flip-flop changes states (low to high, or high to low). The flip flop ignores the low-to-high transition on the input; it only changes on the high-to-low. So, the output switches states at half the rate of the input (a divide by 2 counter).

This is output Q1 (hypothetical) on your 4060 chip. Now, connect that output (Q1) to the input of another toggle flip-flop. Now that 2nd flip flop (Q2) only changes states when Q1 goes from high to low. So you're taking something that was divided by 2 and dividing it by 2 again. The end result is Q2 is the clock signal divided by 4. Each additional stage (flip-flop) divides by 2 yet again.

The 4060 has 14 such flip flops cascaded together, thus it gives you a 14 bit counter. The outputs Q1-14 divide by 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048, 4096, and 8192 respectively. (Q1-3 aren't available on the 4060, so the minimum division available on this chip is 16).

Ripple counters are a basic way to create a binary counter. If you construct one out of separate flip flops, and connect the complementary-Q outputs to the inputs of the next stage (or invert the output before passing it to the next input), you create a ripple counter that counts backwards. That's the principle behind binary up/down counters.
 
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axro

New Member
Thank you very much.

That makes sense with what I am seeing. BUT. Check out this webpage:

http://www.reuk.co.uk/Timer-Circuits-With-4060B.htm

what they are stating is different. Here is an example:

To keep things simple, let's assume the count is increased by one every second. The rightmost bit (the 1's bit) will be off for one second, on for one second, off for one second and so on...


0000000001, 0000000010, 0000000011

The fifth bit from the right (the 16's bit) is therefore off for 16 seconds (when the count is 0-15), then on for 16 seconds (when the count is 16-31), then off for 16 seconds (when the count is 32-47), and so on.
That would seem to be different from what you are saying and I see in my experiements. If the clock is incremented 1 every second then Q4 would be on for 8 seconds and off for 8 second(combining for a total of 16seconds or 1 clock cycle).

They are stating the Q4 would be on for 16seconds and off for 16 seconds. What gives?
 
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MikeMl

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Most Helpful Member
If the period of the clock is 1second, the fifth bit will have a period of 2Λ5=32 seconds, which means it will be low for 16seconds and high for 16 seconds.
 

MikeMl

Well-Known Member
Most Helpful Member
So the website I posted is completely wrong?
Not unusual. A lot of "experts" that put up web pages are better at writing HTML than engineering:D
 

axro

New Member
Interesting, and kinda scary.

So basically what happens is, that each port actually goes high on half of it's value. 16 high at cycle 8. 32 high at cycle 16. 64 high at cycle 32 and so on...

That sound about right?
 

kpatz

New Member
Interesting, and kinda scary.

So basically what happens is, that each port actually goes high on half of it's value. 16 high at cycle 8. 32 high at cycle 16. 64 high at cycle 32 and so on...

That sound about right?
Sort of. What you're describing as "values" are actually the divisions. The (binary) values are 1/2 the divisions. Think of the chip as a binary counter, where low = 0 and high = 1. Q14 is the most significant bit and (internally) Q1 is the least significant. I bolded the bits that are available at the output pins, the 3 least significant bits are maintained internally but aren't brought out to pins.

So, you start with all bits low: 00000000000000
Then with each clock high-to-low transition, the chip counts as follows:

Clock 01: 00000000000001
Clock 02: 00000000000010
Clock 03: 00000000000011
Clock 04: 00000000000100
Clock 05: 00000000000101
Clock 06: 00000000000110
Clock 07: 00000000000111
Clock 08: 00000000001000
Clock 09: 00000000001001
Clock 10: 00000000001010
Clock 11: 00000000001011
Clock 12: 00000000001100
Clock 13: 00000000001101
Clock 14: 00000000001110
Clock 15: 00000000001111
Clock 16: 00000000010000
Clock 17: 00000000010001
Clock 18: 00000000010010
Clock 19: 00000000010011
Clock 20: 00000000010100
Clock 21: 00000000010101
Clock 22: 00000000010110
Clock 23: 00000000010111
Clock 24: 00000000011000
Clock 25: 00000000011001
Clock 26: 00000000011010
Clock 27: 00000000011011
Clock 28: 00000000011100
Clock 29: 00000000011101
Clock 30: 00000000011110
Clock 31: 00000000011111
Clock 32: 00000000100000

Q1 has a binary value of 1 (2^0), and toggles once per clock pulse, so it divides by 2 (you get one high-to-low transition on this bit for every 2 high-to-low transitions on the clock). Q2 has a binary value of 2, and divides the clock pulse by 4. So, the lowest available pin, Q4, has a binary value of 8 and it divides the clock pulse by 16.

The gist of it is, you can look at the chip as either a binary counter (where 11 of the 14 bits are available at the outputs), and you treat the highs and lows as ones and zeroes, or as a divider, where you would only care about the transitions from high to low, not about whether the pin is high or low, nor would you care about low-to-high transitions. Looking at my table above, the first transition from 1 to 0 (high to low) of Q4 occurs after 16 (not 8) clock pulses.
 
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axro

New Member
So what you are saying is that Q4 is acually the 3rd Bit and not the 4th?

I think I may understand where I was getting the confusion. When I did binary in school(IP's and subnet masks) in a 8 bit number the first bit was 0 not 1. So in an 8 bit number it was acutally 0-7 not 1-8. Thats why I was so confused.
 
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kpatz

New Member
So what you are saying is that Q4 is acually the 3rd Bit and not the 4th?

I think I may understand where I was getting the confusion. When I did binary in school(IP's and subnet masks) in a 8 bit number the first bit was 0 not 1. So in an 8 bit number it was acutally 0-7 not 1-8. Thats why I was so confused.
Correct... Q1 is bit 0, Q2 is bit 1, Q4 bit 3, etc.

It's the old "starting from 0" vs. "starting from 1" confusion. ;)
 
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