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Writing a software Interrupt Controller

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electroRF

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Hi,

I have 2 Cores (uCs) in chip.

There's an available General-Purpose Interrupt between the two.

Core A frequently needs to ask Core B to read / Write a certain Register for a module which is only accessible to Core B.

Core B is to perform the Reading / Writing, and return an Acknowledge (with the register Value if in case of a Reading Request).

I'd like to use the General Purpose Interrupt for this purpose.

How would you suggest to efficiently pass Data using this Interrupt?

There's an available Shared Memory, and I'd very love to hear how you would utilize it for this task.

The Challenge here is that Core A might trigger a second Read/Write request to Core B from Task2,
Before Core B finished with the first Read / Write Request from Task1, and I'd need to support such case.

An Example to what I mean:

C:
//Called from Task 1
INT32 Core_A_Func1 (INT32 Address1)
{
    UINT32 Value1;  //Line 1

    Value1 = CORE_B_READ( Address1 ); //Line 2

    return Value1; //Line 3
}

//Called from Task 2
INT32 Core_A_Func2 (INT32 Address2)
{
    UINT32 Value2;  //Line 1

    Value2= CORE_B_READ( Address2 ); //Line 2

    return Value2; //Line 3
}

It could be that While Func1 is waiting for Value1 (in Task 1), Func2 was triggered (from Task 2), and also calls CORE_B_READ, and is waiting for Value2.

How would you implement CORE_B_READ Function?

Thank you very much.
 
Last edited:
Wait until core B is free (done with all other tasks), then do whatever needs to be done and return. Not much choice here.
 
Hi North Guy,
However,
Say that while Task A waits for Core B to return a Value,

Task B is triggered (higher priority then Task A) and also waits for Core B to return a Value.

How do you manage this, for having Task B getting its Value (and not Task A's value), and Task A getting its Value?

How will you manage this Synch?

*Both Tasks are running @ Core A of course.
 
You do not need to manage a sync. You don't even request value B before value A is received. Otherwise, core B must be able to process multiple requests simultaneously.
 
Hi North Guy

Thank you.

Let me explain please.

Task A starts running on Core A, and request Core B to read a certain Address and return its value, call it Value-A .

While it waits for Core B to return the Value,

Task B is triggered and gets the Core-A CPU time.

Now Task A is suspended until Task B is finished.

Task B now asks Core B to read a certain Address and return its value, call it Value-B .

So, Obviously, even though Task A asked for an Address' Value first (from Core B),

Task B will get Value-B before Task A get Value-A.

I'd love to hear how would you handle it?

Thank you very much.
 
How long does it take for core B to return the value? Can you suspend core A until the request is filled?

If not, you would need to write some sort of a server on core B which can serve simultaneous asynchronous requests (sort of like Web server does).
 
I could be wrong here, but it sounds to me like nested vector interrupts. A processor, picking a Cortex M3, for example, takes care of the interrupt vectors and returns in hardware, each interrupt having a priority level set for it. Where I could see your real problem lie, would be if TaskB needed the value returned by TaskA to complete the address look-up. You stated that TaskB has a higher priority than TaskA. It may interrupt the TaskA process before the value is returned by it in order to complete the TaskB look-up :D Of course, there are many processor variants available, but if your processors don't support nested interrupts natively in hardware, then you will need to vector to an interrupt handler of your own design to implement it :)
 
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