Synchronous Counter

[Bullet]

make changes to the synchronous counter diagram so that the new count sequence is 3,4,6,7

Does anyone know how to draw this circuit?
p.s
it's a 3-bit counter

Thanks

 

[MrAl]

Hello,


Where is the original diagram?

 

[Bullet]

The counter

Sorry here it is
Thanks

 

[Ratchit]

Bullet,

make changes to the synchronous counter diagram so that the new count sequence is 3,4,6,7

Have you tried to set up a excitation table? Do you know how to do it? It won't do you much good if we just throw a circuit at you if you have no idea how it was designed.

Ratch

 

[Bullet]

I have drawn out the table but when I try to re-jig the circuit according to the k-maps I just keep coming up with the original count of 7,6,3,4

 

[MrAl]

Hi again,


Thanks for the schematic

Ok, now what kind of gates are you limited to use, can you use any kind of gate you want? I ask because the first thing i noticed was that the circuit posted is capable of attaining 8 distinctly different states, when only 4 states are needed which could conceivably lower the flip flop count to only 2. You might not be able to get away with that because of the timing requirements, but i though i would ask anyway.

 

[Bullet]

Im able to use any gate but must use as few as possible. With my first attempt i used only one AND gate on the k2 and QNot1 on the 1st and 2nd bistable I came to this through the k-maps that I worked out on 3,4,6,7 count sequence but the count still started at the original 7 value.

 

[Ratchit]

Bullet,

Can you post your excitation table which you used to determine the gates and connections for the sequence you desire?

Ratch

 

[Jimmy13]

Has anyone found out the answer to this guys question?

 

[Ratchit]

Jimmy13,

Has anyone found out the answer to this guys question?
​

Certainly, but we don't want to just give him an answer. We want to see what he has done to solve it. So far, the OP has not responded.

Ratch