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PIC hardware I2C & SLEEP power

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Oznog

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I'm using PIC18F's hardware-based SSP I2C interface, and I'm also using the sleep mode in both master & slave. The master goes to sleep when the slave's data indicates the engine is off for awhile. The slave sleeps when it stops receiving I2C transmissions for awhile.

Additionally, this was designed for the cable to be unplugged & plugged (hot plugged) unpredictably.

Now the slave is designed to wake up when a button is pressed on the master, so the SSP module remains on, uninterrupted. The SSP module generates an interrupt which will wake the slave when a new transaction begins. However, the catch appears that sometimes the SSP module on either side could be in a state which actively pulls the SCK or SDA low. Since these use pullup resistors, this presents a battery-killing load during low power Sleep.

The best thing I can think of is to have the Master wait until the I2C response is complete and the bus idle before pulling the sleep. Is there another solution? Can the hot plug issue leave the Slave waiting for a clock from the Master which will never come, performing a pulldown on the bus which will never be answered and thus unable to sleep?
 
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